- 期刊
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
延伸閱讀
- Hsu, T. Y. (2007). A Generalized Network Flow Based Algorithm for Power-Aware FPGA Memory Mapping [master's thesis, National Tsing Hua University]. Airiti Library. https://doi.org/10.6843/NTHU.2007.00611
- Siozios, K., Bartzas, A., & Soudris, D. (2008). Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology. International Journal of Reconfigurable Computing, 2008(), 127-144. https://doi.org/10.1155/2008/764942
- WANG, K. H., CHEN, C., & HWANG, T. T. (1994). Technology Mapping for FPGA Using Generalized Functional Decomposition. VLSI Design, 1994(), 89-103. https://doi.org/10.1155/1994/56371
- Kerkiz, N., Elchouemi, A., & Bouldin, D. (2010). Multi-FPGA Partitioning Method Based on Topological Levelization. Journal of Electrical and Computer Engineering, 2010(), 379-383. https://doi.org/10.1155/2010/709487
- Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. International Journal of Reconfigurable Computing, 2011(), 421-431. https://doi.org/10.1155/2011/760954