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A Fast Algorithm for Performance-Driven Module Implementation Selection

摘要


We develop an O( p log n) time algorithm to obtain optimal solutions to the p-pin n-net single channel performance-driven implementation selection problem in which each module has at most two possible implementations (2-PDMIS). Although Her, Wang and Wong [1] have also developed an O(p log n) algorithm for this problem, experiments indicate that our algorithm is twice as fast on small circuits and up to eleven times as fast on larger circuits. We also develop an O(pn^(c-1)) time algorithm for the c, c > 1, channel version of the 2-PDMIS problem.

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