Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

NIKOS SKLAVOS ； ALEXANDROS PAPAKONSTANTINOU ； SPYROS THEOHARIS ； ODYSSEAS KOUFOPAVLOU

《VLSI Design》 2002卷 (2002/12) Pp. 455-468

https://doi.org/10.1080/1065514021000012066

摘要

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6μm CMOS technology. With a system clock of up to 8MHz and a power supply of 5V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently inWireless Encryption Protocols and high speed networks.

關鍵字

IDEA algorithm ； Cryptography ； Encryption decryption algorithm ； Asynchronous VLSI implementation