Minimizing Spurious Switching Activities with Transistor Sizing

ARTUR WROBLEWSKI ； CHRISTIAN V. SCHIMPFLE ； OTTO SCHUMACHER ； JOSEF A. NOSSEK

《VLSI Design》 2002卷 (2002/12) Pp. 537-545

https://doi.org/10.1080/1065514021000012156

摘要

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows equalizing different path delays without influencing the total delay of the circuit. Unfortunately, not only the delay, but also power consumption circuits depend on the transistor sizes. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence.

關鍵字

Glitches ； Transistor sizing ； VLSI ； Low-power ； CMOS