Performance Driven Global Routing Through Gradual Refinement

JIANG HU ； SACHIN S. SAPATNEKAR

《VLSI Design》 2002卷 (2002/12) Pp. 595-604

https://doi.org/10.1080/1065514021000012219

摘要

We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method.

關鍵字

VLSI ； Deep-submicron ； Interconnect ； Timing-optimization ； Physical-design ； Global routing