A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Jerbi, K., Raulet, M., Deforges, O., & Abid, M. (2012). Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs. VLSI Design, 2012(), 93-106. https://doi.org/10.1155/2012/298396
Wang, H. C., Liu, C. T., & Huang, T. H. (2007). A Concept-Level Ontology Construction Method for Automatic Summarization. 網際網路技術學刊, 8(4), 381-387. https://doi.org/10.6138/JIT.2007.8.4.02
張漢揚（2016）。A Study on Hierarchical Models for Skewed Responses.〔碩士論文，國立臺北大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0023-1303201714250789
Chang, D. W. (2017). Theoretical and Performance Analysis for Integrated Randomized Singular Value Decomposition [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201702973
林陳杰（1994）。An Application of Expert System on Lot-Sizing Models〔碩士論文，元智大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0009-0112200611361744