- 期刊
Performance Modelling and Acceleration of Binary Edwards Curve Processor on FPGAs
並列摘要
Binary Edwards Curve has evolved as an alternative to conventional elliptic curve cryptography which is prone to operational point attacks. However, comparatively slower uni ed scalar multiplication algorithm of this curve poses design challenges to hardware designers. FPGA, as opposed to ASICs due to their speci clook-up-table based underlying architecture, provides unique challenges and opportunities for the design of such complex circuits. In this work, as opposed to an ad-hoc design methodology, we focus on developing an e cient architecture for scalar multiplication on binary Edwards curve in an analytical fashion. The method rstidenties the tunable parameters of the architecture, followed by developing analytical estimates of the resources used and the critical path delay of the circuit in terms of the design parameters and the FPGA characteristics. Detailed analytical and experimental results have been provided to show that the model indeed helps to develop an architecture with improved effciency with respect to other reported results on similar platform.