精密定位技術於先進封裝製程之應用

Applications of Precision Positioning Technology on Advanced IC Packaging Processes

陳孟群 ； 黃振榮 ； 李侃峰

《機械工業雜誌》 411期 (2017/06) Pp. 89-98

摘要

由於IC 元件線寬已達到小於十奈米等級，這些IC 元件的整合與封裝必須採用更短的路徑和導線來連結，降低連線的電阻與電容效應所產生的延遲，才能真正發揮這些元件的效益。加上近年來穿戴式行動裝置的日漸普及，為了達成電子產品體積更小、功耗更低及性能更佳等需求，先進封裝製程如3D/2.5D IC 封裝，近年來技術發展迅速，已成為封裝新趨勢。本文將針對先進封裝製程所需的精密定位技術，主要在晶片堆疊等製程的應用進行探討。

關鍵字

晶片堆疊 ； 矽穿孔 ； 微凸塊

並列摘要

Since the IC circuit linewidth has reached a level less than ten nanometers, the integration and encapsulation of these IC components must adopt shorter interconnection to reduce the delay resulted from the resistance and capacitance effects and reach its best performance. As the popularity of wearable mobile devices is growing, in order to meet the needs of smaller electronic products, lower power consumption and better performance, advanced packaging processes such as 3D / 2.5D IC package has been progressing rapidly in recent years and has become new trends in packaging. This paper will focus on precision positioning technology required in advanced packaging process, mainly in the chip stacking areas.

並列關鍵字

Chip Stacking ； Through Silicon Via ； Micro-Bump

參考文獻

Interconnect Technology Working Group(2013).International Technology Roadmap for Semiconductors, Interconnect.,未出版ITRS Group Ltd.

Chip Stacking for 3D IC, EVG website, https://www.evgroup.com/en/solutions/3d-ic/chip_stacking.

Winters, Jasper(2010).Conceptual design of a pick and place machine for 3D-IC.TU Delft.

黃振榮(2016).高剛性自調精密定位模組.經濟部工業局 105 年度光電及半導體設備產業發展計畫技術開發與輔導計畫書.(經濟部工業局 105 年度光電及半導體設備產業發展計畫技術開發與輔導計畫書).,未出版.

黃振榮(2014).高產出晶片取出模組.經濟部工業局 103 年度半導體設備暨零組件產業發展計畫技術開發與輔導計畫書.(經濟部工業局 103 年度半導體設備暨零組件產業發展計畫技術開發與輔導計畫書).,未出版.