Design of Dynamically Reconfigurable Accelerator for Convolutional Neural Networks

Kaisheng Shi ； Mingwei Wang ； Xin Tan ； Qianghua Li ； Tao Lei

《International Core Journal of Engineering》 9卷3期 (2023/03) Pp. 68-77

https://doi.org/10.6919/ICJE.202303_9(3).0009

摘要

A Dynamically Reconfigurable Accelerator for Convolutional Neural Networks (CNNs) is proposed to address the issues of high power consumption, hardware resource constraints, and low flexibility in deploying CNNs on embedded edge computing devices. Firstly, a general dynamic reconfigurable accelerator architecture is designed using the low‐power, parallel computing, and resource reconfigurable characteristics of Field‐Programmable Gate Arrays (FPGAs). Secondly, the operation modules are designed for reconfigurable modules and parallel computing optimization, generating corresponding configurable bitstream files. The accelerator is then deployed on the heterogeneous platform of ARM and FPGA through software‐hardware co‐design. Finally, the dynamic configuration of the accelerator is completed by controlling and loading different bitstream files from the upper computer, accelerating the forward inference operation of CNNs. Experimental results show that compared to current typical accelerator designs, the proposed approach significantly reduces resource consumption and reduces power consumption, and has a certain application value.

關鍵字

FPGA ； CCN ； Dynamic Reconfiguration ； Hardware Acceleration ； Software Hardware Co‐design

參考文獻

REUTHER A, MICHALES P, Jones M, et al. AI and ML Accelerator Survey and Trends [C] //2022 IEEE High Performance Extreme Computing Conference, Waltham, USA: IEEE,2022:1-10.

ZHANG Jiehe, ZHANG Feng, Xie Min, et al. Design and Implementation of CNN Traffic Lights Classification Based on FPGA[C] //2021 IEEE 4th International Conference on Electronic Information and Communication Technology, Xi’an China, IEEE, 2021: 445-449.

PESTANA D, MIRAND P R, LOPES J D, et al. A Full Featured Configurable Accelerator for Object Detection With YOLO[J]. IEEE Access, 2021, 9: 75864-75877.

Chen Y H, Fan C P, Chang R C. Prototype of Low Complexity CNN Hardware Accelerator with FPGA-based PYNQ Platform for Dual-Mode Biometrics Recognition[C] //2020 International SoC Design Conference, Yeosu, Korea, IEEE, 2020:189-190.

SRIVASTAVA H, SARAWADEKAR K, DEPTHWISE A. Separable Convolution Architecture for CNN Accelerator[C] //2020 IEEE Applied Signal Processing Conference, Kolkata, India: IEEE,2020:1-5.