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基於有限狀態機架構之快速金鑰串流產生器設計

摘要


無線通訊已成為人們日常生活之一環,面對無線網路愈來愈高的頻寬需求,如何快速產生金鑰串流,以有效利用串流加密技術對通訊內容進行加密及解密,可能成為未來維持無線網路通訊安全的一種挑戰。本研究提出基於有限狀態機(FSM)的快速金鑰串流產生器,以解決上述之問題。本研究利用FSM控制多密碼模組同步運作,以快速產生符合串流加密所需之金鑰串流。本方法經硬體描述語言Verilog完成硬體設計,並利用ModelSim模擬軟體完成相關模擬實驗。模擬結果顯示,本方法可有效藉由增加密碼模組之數量以加速金鑰串流之產生,可作為高頻寬環境下,進行無線網路通訊加密及解密之參考。

並列摘要


Wireless communication have become a part of human life. As the demand of growing communication bandwidth, how to quickly generate the key stream to efficiently encrypt and decrypt the communication content can be a challenge for maintaining the security of wireless communication in the future. This study is to propose a finite state machine (FSM) structure based fast key stream generator. We use the FSM structure to control multiple cipher modules to generate enough key stream for performing stream cipher. The proposed method has been designed using the hardware description languish (HDL) Verilog and tested by the simulation tool ModelSim. Simulation results show that the proposed method can efficiently speed up the generation of key stream by adding more cipher modules and, therefore, can be used for in the high bandwidth communication environment.

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