一維雙模提升式離散小波轉換之提高精準度VLSI架構設計

Precise VLSI Architecture Design of 1-D Dual-Mode LDWT

夏至賢(Chih-Hsien Hsia) ； 李子暄(Zi-Xuan Li) ； 魏成恩(Cheng-En Wei)

《中正嶺學報》 45卷2期 (2016/11) Pp. 65-73

摘要

一維雙模提升式離散小波轉換在超大型積體電路架構設計中常因運算時產生訊號誤差影響的問題。有鑑於此，本文改善其硬體架構以解決上述問題並針對其硬體作有效地設計：第一，以乘數與乘積共用暫存器的方式取代了傳統內部所有使用到乘法器部分之架構，達到面積與運算複雜度兩者兼顧的優勢；第二，在考慮提升式架構下因臨界路徑過長所產生硬體運算時間過長的問題，提出平行架構結合管線式架構以解決其VLSI設計的問題。由實驗結果得知，本文所提出上述的混合式VLSI架構可達到降低運算誤差值至5.68%以及提升17%的硬體使用率，適合應用於嵌入式硬體平台。

關鍵字

訊號誤差影響 ； 16×16位元乘法器 ； 離散小波轉換 ； 管線與平行架構處理

並列摘要

1-D Dual-mode Lifting-based Discrete Wavelet Transform (LDWT) often experiences a wordlength effect during computation in Very Large Scale Integration (VLSI). Thus, this work improved the hardware architectures to solve this problem with an effective design. First, common multiplier and product registers replaced all conventional internal multipliers to improve area and computation complexity. Second, to combat long computation times due to long critical paths, parallel and pipeline architectures were combined to solve the VLSI problems. As results, show that the hybrid VLSI architecture proposed in this work could reduce computation errors to 5.68% and increase hardware usage by 17%, making it perfect for embedded hardware platforms.

並列關鍵字

Wordlenght effect ； 16×16 bit multiplier ； Discrete wavelet transform ； Pipeline and Parallel architecture