前瞻金氧半元件研究

摘要本論文中，總共分為兩大論點，分為模擬的部分跟實驗的部分，模擬的部分中主要在鰭式場效體電晶體的電特性與改良，實驗的部分做高介電係數材料的電特性分析。隨著元件越來越小，以及在小元件時氧化矽也越做越薄，使得以後必須製作鰭式電晶體場效體及高介電係數氧化層的材料。在鰭式電晶體場效體的中，我們提出了一些改良，將矽包著鬆弛的矽鍺而使得矽被形變，並且可以讓NMOS FET的特性變得更佳，但是在PMOS FET中由於電洞會在中心通道先導通，導致次臨界斜率沒那麼多有像NMOS FET可以降低。使用高介電係數材料當閘極氧化層為將來挑戰元件越做越小，氧化層越做越薄，使得閘極漏電流越來越大而為了防止閘極漏電流的增加，使用了高介電係數的材料，可讓元件的氧化層不需要做得那麼薄進而改善漏電流的問題，目前所找到適合的為氧化鉿，氧化鉿在眾多氧化物中是最被看好的。在氧化鉿的可靠度方面我們可以利用量測光的可靠度來判斷是否在其介面有過多的缺陷，過多的缺陷會影響發光的品質，所以可以用來判斷。

關鍵字

前瞻金氧半元件研究

並列摘要

Abstract The thesis is divided into two parts, simulation and experiment, which is related to FinFET and electronics of high-k material respectively. Due to the scaling down of the device size, the SiO2 scaling is currently the biggest challenge, which needs to satisfy only a few mono-layers SiO2. FinFET is the one solution to the scaling problem that improves the control of gate. It is very important to model the physics of FinFET with the simulation before achievement of process. The difference between FinFET and Strained FinFET, and the electric characteristics of NMOS and PMOS devices are introduced. Using high-k material as gate insulator is another method to overcome the scaling challenge. The HfO2 is a very promising candidate in several high-k materials due to high thermal stability, wide band gap, acceptable band offset from silicon, and high dielectric constant, as compared to SiO2. The optical and electrical properties of high-k reliability without annealing and that after H2 and D2 annealing are demonstrated the difference between. The optical characteristic of high-k is without a sharp breakdown with D2 annealing. The HfO2 thin films using oxidation of Hf and HfN are prepared on MIS structure, and the electrical characteristics of oxidation HfO2 under different temperatures are discussed. Finally, we made a summary and a future work.

並列關鍵字

Metal-Oxide-Semiconductor Device

參考文獻

[1] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Res. Develop.,

[2] J. A. Hutchby, G. I. Bourianoff, V. V. Zhirnov, and J. E. Brewer, “Extending the road beyond CMOS,” IEEE Circuits Devices Mag., vol. 18,

[3] Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. Develop.,vol. 46, no. 2/3, pp. 213–222, Mar./May 2002.

[4] E. J. Nowak, “Maintaining the benefits of CMOS scaling when scaling bogs down,” IBM J. Res. Develop., vol. 46, no. 2/3, pp. 169–180,Mar./May 2002.

[6] G. Pei et al., “FinFET Design Considerations Based on 3-D Simulation and Analytical Modeling,” IEEE Trans. Electron Device, p.1411, 2002.

國際替代計量

前瞻金氧半元件研究

主題瀏覽