低功率自動掃描測試向量產生

全掃描式電路測試功率消耗已經成為時下最重要的問題之一。過量的測試功率將導致待測電路毀損或是在測試中影響電路的功率完整性而造成錯誤。本論文將提出兩個有效的低功率自動測試向量產生技術，有效的降低全掃描測試功率之峰值功率消耗。在第一個技術中，我們提出同位元追溯、錯誤信號傳輸限制、低功率動態控制係數轉換以及新的未知未明確指明位元填入之技術並有效的將其整合在傳統的測試向量產生流程中。此外，測資重新產生可進一步增加整體的效果。根據較大的ISCAS89測試電路的結果顯示，我們的技術可以成功將信號掃描時的峰值功率降低達26%以及峰值信號擷取功率達31%。而所造成的測試資料長度的增加僅有11.2%。而第二個技術中，我們提出解決因為功率過大而造成電路的功率完整性降低的可行解決方案。我們引入整數式線性規劃和亂數模擬的技術有效的降低測試峰值功率。實驗結果顯示我們能有效的降低信號掃描峰值功率達35%且同樣的技術可同時拿來用於減少信號擷取功率。此外在這個技術中所增加的測試長度非常小。

關鍵字

低功率測試；掃描式電路；未明確指明位元填入；功率完整性；數式線性規劃

並列摘要

Power dissipation is a serious problem for scan-based testing because it can cause catastrophic damaging of circuit under test or degrade power integrity during test. This thesis proposes two effective low power automatic test pattern generation (ATPG) flows to reduce the peak power during scan-based testing. The first technique is CASPR, Capture and Shift Power Reduction. It includes parity backtrace, confined fault propagation, dynamic controllability, X-filling procedure for both shift and capture, and test regeneration and all techniques of CASPR can be integrated to conventional test generation flow. The experimental data on ISCAS89 benchmark circuits show that CASPR succeed to reduce the peak capture power by 31% and peak shift power by 26% in single stuck at fault test pattern generation with only 11.2% test length overhead. The second technique called CASTR, Capture and Shift Toggle Reduction, proposes a new low power test generation flow to handle the exceeded power noise problem during testing. Exceeded power noise can degrade power integrity and increase the probability of yield loss. We combine both pseudo boolean optimization and random simulation flow into X-Constraint ATPG. Moreover, a modified test regeneration procedure based X-identification techniques is also introduced to further improve the results. In the experimental results, we can reduction the peak shift flip-flop transition count (FFTC), which is showed to be highly correlation with power noise, by 35% with negligible test length overhead by CASTR. The same technique can also be applied for peak capture FFTC reduction.

並列關鍵字

low power automatic test pattern generation (LP-ATPG) ； Scan-based Testing ； X-filling ； power noise problem ； Pseudo Boolean Constraint (PBC)

參考文獻

[Butler 04] K. M. Butler, J. S. A. Jain, T. F. Jack Lewis, and G. Hetherington, ”Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” Proc. IEEE Int’l Test Conf., pp77-84, 2004.

[Cho 06] Minsik Cho and Pan, D.Z., “PEAKASO: Peak-Temperature Aware Scan-Vector Optimization,” Minsik Cho; Pan, D.Z. VLSI Test Symposium, 2006. Proceedings. 24th IEEE Volume , Issue , 30 April-4 May 2006 Page(s):

[Dvanathan 07] V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Variation-Tolerant, Power-Safe Pattern Generation. IEEE Design & Test of Computers 24(4): 374-384 (2007).

[Fujiwara 83] H. Fujiwara and T. Shimono, “On the acceleration of test generation

[Girard 02] P. Girard , “Survey of Low-Power Testing of VLSI Circuits,” IEEE Des. and Test of Comput., pp. 82-92, May-June 2002.

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低功率自動掃描測試向量產生

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