利用反覆估計及去除剪波雜訊的正交分頻多工系統之積體電路設計

An IC Design of the OFDM Transceiver with Iterative Estimation and Cancellation of Clipping noise

陳治中(Chih-Chung Chen)

指導教授 ： 林茂昭

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.00042

摘要

本論文根據Hangjun Chen 和 Alexander M. Haimovich 所提出使用正交分頻多工系統架構去建立一個系統機積體電路設計。系統規格為編碼速率1/2的迴旋編碼器、16-QAM調變器、隨機交錯器、剪波器、長度64和256的FFT/IFFT以及維特比解碼器，還有傳輸的載波長度為64的長度。主要設計了FFT/IFFT模組和剪波器，同時也完成其餘的模組，已完成整個傳送器和接收器系統。使用的工具是Verilog HDL 進行實作，並以C語言進行RTL的模擬和驗證。本論文設計的傳送端所用的運算邏輯單位(ALU)為26,066，邏輯閘暫存器(logic register)為35,130及記憶體位元為32,801而接收端所用的運算邏輯單位(ALU)為33,779，邏輯閘暫存器(logic register)為40,379及記憶體位元為34,413。

關鍵字

OFDM ； 剪波器 ； 積體電路設計

並列摘要

In this thesis, the design issues of the orthogonal frequency division multiplexing (OFDM) system that Hangjun Chen and Alexander M. Haimovich proposed are addressed. The system specifications are the convolutional encoder with code rate 1/2, 16-QAM modulation, random interleaver, clipping, 64-point/256-point FFT/IFFT, and Viterbi decoder. The number of subcarriers is 64 in the system. The mainly modules including FFT/IFFT, and Clipping, have been integrated with several other modules to constitute the OFDM system. This system has been implemented by Verilog HDL and verified against with C-bases behavior model. The implement results shows that the design of the transmitter uses 26,066 arithmetic logic units (ALU), 35,130 logic registers, and 32,801 memory bits and the design of the receiver uses 33,779 arithmetic logic units (ALU), 40,379 logic registers, and 34,413 memory bits.

並列關鍵字

OFDM ； Clipping ； VLSI

參考文獻

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