考慮可繞性與電源供應之超大型積體電路擺置

擺置在實體設計中扮演相當重要的角色。雖然擺置技術已經被研究了數十年，現代設計的挑戰，例如可繞性及電源功率消耗，要求電路設計者發展一個更具彈性的擺置演算法。然而，大多數傳統的擺置演算法通常集中注意力在線長最佳化而忽略了實際上的設計問題，如電源供應完整性與可繞性。此外，由於電子應用的進步，減少功率消耗逐漸在電路設計中變成一個不可或缺的考量，但是大部分的擺置演算法仍然沒有針對這點做最佳化。在電路擺置的過程中考慮這些因素可以有效減少後續實體設計流程的負擔 (如繞線、電源供應微調、等等)，並且可以改善電路設計完整性。在這份論文當中，我們提出了數個演算法在產生超大型積體電路擺置的同時，考慮電源供應完整性與可繞性。我們提出一個結合快速電壓分析技術的電源供應完整性 (特別針對電壓壓降) 擺置演算法，以降低違反壓降限制的數量。之後我們利用設計階層的資訊幫助擺置演算法最佳化可繞性，此外，我們還討論了如何能同時得到一個較佳的壓降和可繞性的擺置結果。實驗結果顯示我們提出的電壓壓降及可繞性擺置演算法比之前的相關研究可以分別得到較小的壓降及繞線失敗。另外，隨著功率消耗成為不可或缺的考量，有許多技術紛紛被提出以降低功率消耗。在這些技術中，使用脈衝栓鎖逐漸成為一個受歡迎的技術，相較於傳統的正反器，脈衝栓鎖是一種擁有較小延遲及功率消耗儲存資料的元件，他們被廣泛應用在目前高效能的微處理器上。在這份論文中，為了在擺置時降低功率消耗，我們首先提出了一個考慮脈衝栓鎖擺置技術以探索如何能在一個數學解析擺置演算法上有效利用脈衝栓鎖以維持栓鎖的時序完整性。之後，我們提出一個整合擺置及時脈網路合成技術以降低時脈網路的功率消耗並同時維持脈衝栓鎖的時序完整性。實驗結果驗證了我們提出的脈衝栓鎖擺置及共同合成技術在脈衝栓鎖電路設計上的有效性。

關鍵字

實體設計；擺置；電壓壓降；可繞性；電源；脈衝栓鎖

並列摘要

Placement plays a crucial role in the physical synthesis for circuit designs. Although the placement problem has been discussed for decades, modern design challenges, such as routability and power, have demanded circuit designers to develop a more flexible placer. Unfortunately, most existing placement algorithms still focus on optimizing wirelength alone while ignoring design-related issues, e.g., power integrity and routability. Moreover, due to the advance of electronic applications, power consumption is becoming an essential metric in a design, which is not addressed in most placement algorithms either. Considering these issues when optimizing a placement can effectively reduce the burden of subsequent physical synthesis procedures (i.e., routing, power refinement, etc.) and thus improve the design closure. In this dissertation, we propose novel algorithms for VLSI placement problems to consider power integrity and routability. We present power-integrity (voltage-drop, in particular) aware analytical placement along with efficient voltage analysis to reduce voltage-drop violations. Then we utilize design-hierarchy information to guide the placer for routability optimization, and we also discuss how to obtain a better trade-off between voltage drops and routability. Experimental results show that our proposed voltage-drop aware placement and routability-driven lacement can achieve respective smaller voltage drops and routing overflows than previous works. Moreover, as power consumption becomes an essential metric, many techniques have been proposed for power reduction. Among which, pulsed-latches have emerged as a popular technique. Compared with a traditional flip-flop, a pulsed-latch is a sequential device with smaller delay and power, which is extensively adopted in modern high-performance microprocessors. In this dissertation, to address power reduction in placement, we first propose pulsed-latch aware placement to explore how to utilize pulsed-latches in an analytical placer for maintaining their timing integrity. After that, we present unified placement and clock-network co-synthesis to reduce the power consumption of a clock network while maintaining the timing integrity of pulsed-latches. Experimental results validate our pulsed-latch aware placement and co-synthesis approach effectiveness on timing integrity and power reduction for pulsed-latch-based designs.

並列關鍵字

Physical Design ； Placement ； Voltage Drop ； Routability ； Power ； Pulsed-Latch

參考文獻

[3] ISPD 2006 Placement Contest. http://www.sigda.org/ispd2006/contest.html.

clustering technique for VLSI circuit placement. In Proceedings of ACM International

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.

In Proceedings of IEEE/ACM International Conference on Computer-Aided

of design techniques to improve speed and robustness in embedded microprocessors.

國際替代計量

考慮可繞性與電源供應之超大型積體電路擺置

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