晶圓製造優先混合比例規劃之研究

Research on Priority Mix Planning for Semiconductor Fabs

蘇信旭(Shin-Shyu Su)

指導教授 ： 張時中

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.00051

摘要

在不同優先等級下有效地提供製造服務是半導體供應鏈管理的要項之一。比起低優先順序之顧客，高優先順序之顧客付更高的價錢要求更短的產品交期。由於晶圓廠需要龐大的投資且在製造中所占週期時間最長，在半導體供應鏈中有關鍵地位，因此半導體廠中的優先混合比會對製造服務績效，如產出、週期時間(Cycle Time)、在製品量(WIP)、瓶頸位置等等，有顯著影響。
眾多的半導體廠指標中，產品生產週期時間對於晶圓廠的生產力學習與顧客的服務率有重大的影響。為了管理與量測週期時間，我們使用標準化的週期時間:X-因子(X-Factor)，其定義為周期時間(Cycletime)除以總處理時間(Raw processing time)。在實務上，X-因子已證實是一個敏感的指標，並且提供有不同總處理時間產品間相同的比較基準。各優先順序的X-因子(Priority X-Factor, PXF)是各優先順序晶圓投料率、產品製造步驟時間需求與瓶頸機台使用率之函數。在半導體廠製造服務規劃上，對不同優先順序來設定X-因子可以差異化個別機器群生產績效與整廠製造服務表現。
在本論文中，為了提供規劃工具，我們建立數學模型並研究半導體製造優先順序混合比例規劃問題，用來決定各優先順序投料率，在滿足PXF與產能限制下，得到最大化利益(收益-庫存與製造成本)。為了分析半導體廠PXF，陳科竹(2006)發展了一個排隊網路為基礎的模型，重點放在研究優先順序、生產投料、機台特性與產能利用率對PXF之影響。其中以M/G/1: PR 排隊模型來近似單一機台PXF行為，再以PXF貢獻理論建立機台間產流的網路連結模型，得到全廠PXF的網路模型，再針對M/G/1:PR所帶來的誤差，提出修正方案。以此模型為基礎，我們推展至多機台狀況的M /G/m:PR模型，並且將以製程小時為單位之價格與成本結構與加入PMP問題目標函數。
針對普瓦松(Poisson)程序近似抵達程序之誤差，我們比較PXF模型與模擬在各node XF表現值。我們得到變化半導體廠表現對於影響誤差之因素:到達晶圓之來源機台種類、優先順序高低、到達晶圓之來源機台服務時間分佈。模型補償被用來修正普瓦松(Poisson)程序近似抵達程序所造成之誤差。
給予價格與成本結構下，優先順序混合比例規劃問題被發展成非線性規劃問題。我們使用最佳化軟體Lingo來解，目前沒有發展出演算法解；實際上，考量之優先順序層級越多，計算時間越長；而XF有封閉型式之優點，因此計算時間不會大量上升。因此PXF模型用於PMP問題，在真實半導體廠應用上極具價值。
在透過比較模擬與近似之PMP問題解之後，我們探討與分析解PMP問題相關之議題。我們以FAB3出發，僅改變部分因子。固定瓶頸機台使用率與單位製程時間價格與成本。
1. 產品製造步驟-最佳PM； P1具越多製程步驟，優先混合比越低。2. 工作負載-最佳PM；變化P1工作負載時，會使最佳PM先上升在下降。3. PXF限制變化-最佳PM；PXFT組合越大，會分配較多產能給予優先順序1。若分配產能過多造成瓶頸轉移，則分配的產能會減少。總結此論文的貢獻如下:
1. 擴充M/G/m:PR並且串連以形成PXF模型。
2. 驗證PXF 模型並且針對誤差項補償
3. 在考慮多步驟產品下，探討優先順序混合比例規劃問題。
4. 提供考量優先順序、價格成本結構、產能利用率、庫存成本、製程步驟等的規劃工具

關鍵字

優先順序 ； X-因子 ； 循環時間 ； 晶圓製造 ； 產能分配 ； 規劃工具

並列摘要

Effective provision of manufacturing services in multiple priority levels has been one critical aspect to the semiconductor supply chain management. A customer order with a higher priority level demands for a shorter cycle time and pays a higher price than those of orders in a lower priority. Fabs play a critical role because they require the most intensive capital investment and the longest cycle time among all manufacturing phases. The priority mix of a fab significantly affects its performance such as throughput, cycle time, wafer-in-process (WIP) and bottleneck location.
Among the many fab performance indices, cycle time(CT) has a significant impact on productivity learning and customer serviceability. To measure and manage CTs, the notion of X-factor (XF), which is defined as the CT divided by raw processing time (RPT), has been introduced to be a sensitive performance indicator and is standardized across different products. The XF of each priority (PXF) is a function of release rates, processing flow requirements of individual priorities and bottleneck tool group utilization. In production planning of a fab, different XF target (XFT) specifications for individual priority levels of manufacturing services can be set to allow performance differentiation among machine groups of different characteristics and to specify the overall fab performance as well.
In this thesis, we formulate mathematical model and study PMP problem of semiconductor manufacturing, which determines the wafer release rates of individual priorities that maximize the fab profits (revenue minus manufacturing and inventory costs) subject to PXFTs and capacity constraints. Ke-Ju Chen, 2006, developed a queueing network based model. His modeling methodology is focused on capturing how operation priority, production flow variations, and capacity utilizations may affect individual PXFs of a fab. The M/G/1:PR queue model is adopted to model the behavior of a service node (tool group). Then, a PXF contribution theory relates PXFs of individual service nodes to the overall fab PXF and provides a novel priority network model. We extend multi-machines scenario into M/G/m:PR and add multi-products based price-cost structure into the objective function of the PMP problem formulation.
For Poisson process assumption, we compare PXF and simulated results which show the following factors which may affect the PXF errors: 1. The kinds of MG which arrival wafers come from, 2. Priority level, 3. The service time distribution of the MG which arrival wafers come from. Model fitting is then adopted to compensate, for each priority, the errors caused by assuming Poisson arrival process.
Under a given price and cost structure, a PMP problem is formulated as a nonlinear programming problem. We use optimal software Lingo and do not formulate an algorithm. Involving more priority levels will lead to long calculation time. Due to the close form of M/G/m:PR model, the calculation time will not increase significantly. That proves the value for the application on semiconductor fabs.
After validation by simulation of a realistic fab example, we change the variable of FAB3 to numerically study the planning issues. Bottleneck utilization, price and cost structure is fixed:
1. Product process flow - optimal PM: With P1 with more complicated process steps makes PXFs reach targets at lower PM.
2. Total workload - optimal PM: Low P1 workload makes PXF1 reach target at low PM, an high P1 workload also does. As a result, we can find optimal workload for P1 to obtain the maximum PM.
3. PXFT sets - optimal PM: For the bigger PXFT sets, we will increase PM. And due to the bottleneck shifting resulted from too high PM, the PM will be adjusted a little lower. Summarize the contributions of this thesis:
1. Extended M/G/m:PR and constructed PXF model
2. Validated and compensated PXF model
3. Formulated PMP problem which considering multi-steps products
4. provided a planning tool which involve priority, price and cost structure, capacity utilization, WIP, process steps.

並列關鍵字

Priority ； X-factor ； cycletime ； semiconductor manufacturing ； capacity allocation ； planning tool

參考文獻

[ChC06] S. C. Chang, K. J. Chen, “Priority X-Factor Modeling for Differentiated Manufacturing Service Planning,” Proceedings of 2006 International Symposium on Semiconductor Manufacturing, Tokyo, Japan, Sept. 25-27, 2006, pp. 53-56.

[CLH02] S. H. Chung, A. H. I. Lee, C. Y. Huang, and C. C. Chuang, “Capacity Pricing Mechanism for Wafer Fabrication,” Proceedings of 2002 Asia-Pacific Industrial Engineering and Management Symposium, Taiwan, Taipei, Dec. 18-20, 2002, pp. 58-59.

[DSF06] D. Delp, J. Si, and J. W. Fowler, “The Development of the Complete X-Factor Contribution Measurement for Improving Cycle Time and Cycle Time Variability,” IEEE Transactions on Semiconductor Manufacturing, New York, Aug. 2006, pp.352-362.

[HuC04] M. D. Hu, S. C. Chang, “Translating Overall Production Goals into Distributed Flow Control Parameters for Semiconductor Manufacturing,” Journal of Manufacturing Systems, 2003, pp. 46-63.

[LRK94] S. H. Lu, D. Ramaswamy, and P. R. Kumar, “Efficient Scheduling Policies to Reduce Mean and Variance of Cycle-Time in Semiconductor Manufacturing Plants,” IEEE Transactions on Semiconductor Manufacturing, Aug. 1994, pp. 374-388.