支持軟體自我測試之快速且準確之多層級延遲錯誤模擬器

A Fast and Accurate Multilevel Delay Fault Simulator for Software-based Self-Testing

陳匯尊(Hui-Tzuen Chen)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800776

摘要

由於技術的不斷擴展，現代 CPU 中的可靠性問題 (Reliability) 越來越受到人們的重視，原因是老化效應 (Aging effect) 在數十年後可能影響電晶體的性能。為了偵測老化造成的延遲錯誤 (Delay fault), 需要進行在速軟體自我測試 (At-speed software-based self-testing)。過去已有許多在不同抽象層級的軟體自我測試模擬方案被提出，這些方案在速度和精確度之間有不同程度的權衡。本文提出了可支持軟體自我測試架構的功能性延遲錯誤模擬器 (Functional delay fault simulator)。該模擬器主要跑微結構的模擬 (Micro-architectural simulation)，並有條件的切換至邏輯閘層級模擬 (Gate level simulation)來高速且準確地模擬延遲錯誤。為了評估所提出的模擬器，我們提取了在 ARM 指令集 CPU 的 ALU 模組中的路徑，並討論了錯誤啟動 (Fault activation) 行為以及報告測試程式的錯誤覆蓋率 (Fault coverage)。

關鍵字

錯誤模擬器 ； 軟體自我測試 ； 老化效應 ； 路徑延遲錯誤 ； 可靠性 ； 多層級

並列摘要

Due to technology scaling, the reliability issue in modern CPU is increasingly important and is widely discussed since aging effect can affect transistor performance after decades. In order to detect aging-induced delay faults, at-speed software-based self-testing (SBST) is needed. Simulation-based schemes for SBST at different abstraction levels have been proposed, and these works entailed different tradeoff between speed and accuracy. In this thesis, we propose a functional delay fault simulator that supports SBST infrastructure. The proposed simulator mainly runs micro-architectural simulation and conditionally switches to gate level simulation to accurately simulate delay faults with high speed. To evaluate the proposed simulator, we extract paths in ALU module of ARM instruction set CPU, and we discuss fault activation behavior and report fault coverage of test programs.

並列關鍵字

Fault simulator ； Software-based self-testing ； Aging effect ； Path delay fault ； Reliability ； Multilevel

參考文獻

[1] D. Lorenz, G. Georgakos and U. Schlichtmann, "Aging analysis of circuit timing considering NBTI and HCI," 2009 15th IEEE International On-Line Testing Symposium, Sesimbra, Lisbon, 2009, pp. 3-8.

[2] C. Nunes et al., "Aging Effects Analysis in Flip-Flops."

[3] E. J. McCluskey, "Built-In Self-Test Techniques," in IEEE Design & Test of Computers, vol. 2, no. 2, pp. 21-28, April 1985.

[4] M. Psarakis, D. Gizopoulos, E. Sanchez and M. Sonza Reorda, "Microprocessor Software-Based Self-Testing," in IEEE Design & Test of Computers, vol. 27, no. 3, pp. 4-19, May-June 2010.

[5] U. Gunneflo, J. Karlsson and J. Torin, "Evaluation of error detection schemes using fault injection by heavy-ion radiation," International Symposium on Fault-Tolerant Computing, 1989, pp. 340-347.