毫米波高功率及高效率功率放大器之設計

Design of Millimeter-Wave High Output Power and High Efficiency Power Amplifiers

張洋(Yang Chang)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201900742

摘要

本論文總共分成三大部分，第一部分是一個V頻段的疊接組態(cascode)功率放大器，使用65奈米互補式金屬氧化物半導體製程來設計。第二部分是一個Ka頻段的堆疊式(stack)功率放大器，也使用65奈米互補式金屬氧化物半導體製程來設計。最後一部分是一個K頻段且使用新的中和穩定技術(neutralization)的高輸出1dB功率壓縮點(OP1dB)共汲極功率放大器，使用90奈米互補式金屬氧化物半導體製程來設計。
在第一部分，提出了一個是V頻段的高功率、高效率且高增益的三級的功率放大器。一個新提出的疊接組態功率放大器被用來最佳化輸出級的大訊號特性。同時，使用了一個四路的輻射狀變壓功率結合器加上一條低阻抗傳輸線，因此功率放大器的輸出功率可以非常有效率的結合。此提出的V頻段功率放大器在60 GHz達到23.7 dBm的飽和輸出功率、22.1%的最大功率附加效率和29.7 dB的增益，晶片面積為0.653 mm^2。
在第二部分，提出了一個Ka頻段的高功率、高效率且小晶片面積的一級堆疊式功率放大器。為了要達到高輸出功率，使用堆疊三顆電晶體的技術。此外，利用了一個並聯在汲極和源極的回授電容來讓在堆疊三顆電晶體功率放大器裡的各個電晶體的汲極和源極之間的輸出電壓分配平均，因此不只提升了大訊號特性，也提升了長期可靠度。此提出的Ka頻段功率放大器在38 GHz達到24.8 dBm的飽和輸出功率、24.3%的最大功率附加效率和17.5 dB的增益，晶片面積為0.146 mm^2。
在最後一部分，提出了一個K頻段且使用新的中和穩定技術(neutralization)的高輸出1dB功率壓縮點(OP1dB)共汲極功率放大器。因為共汲極放大器高線性度的特性，此提出的共汲極功率放大器在K頻段可以達到高輸出1dB功率壓縮點(OP1dB)。此外，也引入一個新的共汲極放大器中和穩定技術(neutralization)來改善整體的穩定度和增益，所以此提出的互補式金屬氧化物半導體製程的共汲極功率放大器在所有互補式金屬氧化物半導體製程的共汲極功率放大器設計中可成功地第一次操作在高於10 GHz的地方。此提出的共汲極功率放大器在23 GHz達到22.9 dBm的飽和輸出功率、24.2%的最大功率附加效率、22.5 dBm的輸出1dB功率壓縮點(OP1dB)、22.5%的輸出1dB功率壓縮點(OP1dB)之附加效率和10.3 dB的增益，晶片面積為0.479 mm^2。

關鍵字

互補式金屬氧化物半導體 ； 功率放大器 ； K頻段 ； Ka頻段 ； V頻段

並列摘要

This thesis consists of three parts. The first part is a cascode power amplifier (PA) designed at V-band in 65-nm CMOS process. The second part is a stacked PA designed at Ka-band in 65-nm CMOS process. The last part is a K-band high OP1dB common-drain (CD) PA with new neutralization in 90-nm CMOS process.
In the first part, a V-band high output power, high efficiency and high power gain 3-stage PA is proposed. The introduced cascode amplifier is used to optimize the power performance of power stage. Meanwhile, a four-way radial transformer power combiner with a low impedance transmission line is adopted; hence the output power of the PA can be combined with remarkable efficiently. The proposed V-band PA achieves saturated output power of 23.7 dBm, peak power added efficiency (PAE) of 22.1% and power gain of 29.7 dB at 60 GHz with 0.653-mm^2 chip size.
In the second part, a Ka-band one-stage stacked PA with high output power, high efficiency and small chip area is proposed. In order to achieve high output power, 3-stack technique is applied. Moreover, a shunt feedback drain-source capacitor is utilized to make the output voltage divide equally between drain and source of each individual transistor in three-stack PA, which enhances the power performance and the long-term reliability as well. The proposed Ka-band PA achieves saturated output power of 24.8 dBm, peak PAE of 24.3% and power gain of 17.5 dB at 38 GHz with 0.146-mm^2 chip size.
In the last part, a K-band high OP1dB CD PA with new neutralization is proposed. Owing to high-linearity CD amplifier, the proposed CD PA can achieve high OP1dB at K-band. Furthermore, a new neutralization technique for the CD amplifier is introduced to improve overall stability and power gain as well so that the proposed CMOS CD PA can successfully operates above 10 GHz for the first time of the CMOS CD PA design. The proposed CD PA achieves saturated output power of 22.9 dBm, peak PAE of 24.2%, output 1-dB compression point (OP1dB) of 22.5 dBm with PAE of 22.5% and power gain of 10.3 dB at 23 GHz with 0.479-mm^2 chip size.

並列關鍵字

CMOS ； Power amplifier ； K-band ； Ka-band ； V-band

參考文獻

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