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  • 學位論文

基於最佳化分析的射頻功率放大器單一數位預失真技術

Optimization-Based Single Digital Predistortion Technique for RF Power Amplifiers

指導教授 : 劉俊麟

摘要


大規模天線系統預計能提高未來無線通信系統的能源效率,而發射器中最耗电的元件是功率放大器,它可以將訊號功率增强到所需要的水平,因此功率放大器的功率效率需要很高。為了提高小型低成本功率放大器的能量效率,需要將功率放大器驅動到靠近飽和的區域,但由於功率放大器的飽和特性會導致傳輸訊號產生非線性失真,此失真的訊號不僅會降低傳輸訊號的質量還會干擾到相鄰通道的傳輸,因此如何在保持良好功率效率的同時有效地降低功率放大器的非線性失真在近年來是一個備受關注的研究問題。 本篇論文的貢獻主要分成兩個部分,第一個部分我們透過新穎的分析方法為Saleh模型的功率放大器設計相對應的數位預失真器,眾所皆知Saleh模型對於建模高度非線性的功率放大器有較高的準確度,例如行波管放大器。雖然在過往的文獻中已經有方法針對在單一天線的情況下建構數位預失真器,但一般而言混合波束成形大規模天線發射機在天線子陣列中包含多根天線,因此本篇論文將我們的分析方法擴展到多天線的應用,並提出了一種新的數位預失真處理技術。數值模擬的部分說明了整體數位預失真系統的線性化性能得到改善。 本篇論文的第二部分我們考慮了由記憶多項式模型建模的的功率放大器,該模型常用於對固態功率放大器進行建模。在過往的文獻中已經存在對多天線的預失真處理和學習技術,該方法透過組合每個功率放大器的輸出訊號,從而使預期接收器方向上的訊號非線性失真最小化,但應用於更新數位預失真器的多項式係數是眾所皆知的block-LMS參數學習方案,該方案在參數的選擇上不夠穩健。本篇論文提出了一種新的數位預失真參數學習方案,當參數的選擇偏離最佳參數時,整體預失真系統的線性化性能並不會下降太快。數值模擬的結果也說明我們的參數學習解決方案可以補償由記憶功率放大器引起的非線性失真。

並列摘要


Large-scale antenna systems are expected to enhance energy efficiency in future wireless communication systems. The most power hungry components in the transmitter are the power amplifiers (PAs) which strengthen the power of signals to the desired levels. Therefore, the power efficiency of the PAs needs to be high. In order to improve the energy efficiency in small and low cost PAs, it has been suggested to drive the PAs close to saturate region. However, due to the saturation property, the nonlinear distortions introduced by the PAs not only degrade the quality of the transmitted signals but also interfere the transmission of adjacent channels. Recently, how to effectively mitigate the nonlinear distortions of PAs while maintaining good power efficiency is a highly concerned research problem. The contribution of this thesis is mainly divided into two parts. The first part focuses on designing a digital predistortion (DPD) structure for the power amplifiers modeled by Saleh model through a novel analysis method. It is known that Saleh model has high accuracy when it is used to model high nonlinearity PA, such as traveling tube power amplifiers (TWT-PAs). While there are methods to construct the DPD structure for the case of a single antenna, in general, the hybrid beamforming large-scale antenna transmitter contains multiple antennas in an antenna sub-array. This thesis proposes a novel DPD processing technique by expanding our method to multiple antennas. Numerical simulation shows the improved linearization performance of the overall DPD system. The second part of this thesis considers the PA modeled by memory polynomial (MP) model, which is commonly used to model solid-state power amplifiers (SSPAs). There exists the DPD processing and learning technique for the multiple antennas by utilizing a combined signal of the individual PA outputs, which results in minimizing the nonlinear distortion in the direction of the intended receiver. However, the well-known block-LMS parameter learning solution is used to update the polynomial coefficients of digital predistorter, which is not robust enough in the selection of parameter. This thesis proposes a new DPD parameter learning solution, which leads to the better performance when the selection of parameter deviates from the optimal parameter. Simulation results demonstrate that our parameter learning solution can also compensate for the nonlinear distortion caused by the memory PA.

參考文獻


M. Abdelaziz, L. Anttila, A. Brihuega, F. Tufvesson, and M. Valkama. Digital predistortion for hybrid MIMO transmitters. IEEE J. Sel. Topics Signal Processing., 12(3):445–454, Jun. 2018.
M. Abdelaziz, L. Anttila, A. Kiayani, and M. Valkama. Decorrelation-based concurrent digital predistortion with a single feedback path. IEEE Transactions on Microwave Theory and Techniques, 66(1):280–293, Jan. 2018.
H. AlKanan and F. Li. A simplified accuracy enhancement to the Saleh AM/AM modeling and linearization of solid-state RF power amplifiers. Electronics, 9(11):1806, Jun. 2020.
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A. R. Belabad, S. Sharifian, and S. A. Motamedi. An accurate digital baseband predistorter design for linearization of RF power amplifiers by a genetic algorithm based Hammerstein structure. Analog Integrated Circuits and Signal Processing, 95(2):231–247, Jan. 2018.

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