在異質多核心平台的省電排程

A Power Efficient Scheduler for Asymmetric Multi-core Platform

李翔昕(Hsiang-Hsin Li)

指導教授 ： 劉邦鋒

共同指導教授 ： 吳真貞(Jan-Jan Wu)

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201601864

摘要

在計算平台的最新發展趨勢從同質多核心架構轉移到異構和非對稱多核心架構。因此，新的非對稱多核心平台變成一個重要的議題。然而，大多數現有的排程器著重在如何區分合適的工作負載到那些節能的小核心和性能的大核心上。但是並沒有考慮在非對稱多核心上，以合適的核心頻率下分配工作。
在這篇論文中，在非對稱多核心下，我們提出一個對保證工作產量的省電排程器。我們的排程器不僅能決定每個核心的頻率和指派工作來達成減少電量消耗，而且能保證每個工作的產量。從實作結果中，與常見的完全公平排程器相比，我們提出的排程器省下了29 % 的電量。

關鍵字

省電 ； 節能 ； 排程 ； 非對稱多核心 ； 動態電壓調節 ； 動態時脈調節 ； 保證工作產量

並列摘要

A recent trend in computing platforms is moving from homogeneous multicore architectures toward heterogeneous and asymmetric multi-core. Therefore, the design of new schedulers for asymmetric multi-core platform has become an important issue. However, most of the existing schedulers focus on how to distinguish workloads suitable for performance “big” cores from those for power-efficient “little” cores, without considering how to distribute tasks to asymmetric cores running at adjustable frequency.
In this paper, we propose an energy-efficient scheduler for throughput guaranteed tasks running on asymmetric multi-core platforms. The proposed scheduler not only determines the frequency of cores and task assignment in order to reduce energy consumption, but also schedules the tasks so that the throughput of all tasks are guaranteed. The implement results indicate that the proposed scheduler consumes 29% less energy than the conventional Compeletely Fair Scheduler with DVFS enabled.

並列關鍵字

Energy-efficient ； Scheduling ； Asymmetric multi-core ； Throughput Guaranteed Tasks

參考文獻

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