透過您的圖書館登入
IP:3.144.48.13
  • 學位論文

後繞線優化之光學模擬微影缺陷自動修正流程

An Automatic Optical-Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization

指導教授 : 陳少傑
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


光學近似校正(OPC)可以說是當IC的製造步入65奈米及以下的先進深次微米製程之時,IC 設計及製造最具挑戰性的部份。在90奈米及其以上的製程時,使用繞線器(Router)中的各種設計法則(Design Rule)與後繞線時期光學近似校正可以生產出被良好曝光的佈局(Layout)。然而因為下一代的曝光技術上的發展上遇到了無法突破的物理限制,在65奈米及其以下的製程中,僅僅使用設計法則及光學近似校正已經無法在合理的時間之內產生可以良好曝光的佈局。因此,設計者必須在繞線之後進行微影規範檢查(LCC)及微影熱點(Lithography Hotspot)修正。此微影熱點定義為很難被設計法則和光學近似校正所修正之佈局缺陷。如何修正這些微影熱點是一大挑戰,而目前商業EDA設計軟體已經提供了樣式比對(Pattern Matching)的方法。然而,樣式比對不但必須先對於大量各種可能的樣式做實驗,之後還得將樣式及其修正方法存在資料庫之內以供修正時比對之用。這樣的解決方案不但費時、很耗儲存資源,且所建的樣式無法窮盡所有可能微影熱點的樣式,因而修正比例偏低。 在本論文中,我們提出了一個基於光學模擬的自動化的微影熱點修正演算法,並且結合業界的微影熱點偵測工具成為一個完整的後繞線優化之自動修正微影熱點的設計流程。 我們改進了傳統的單調合成(SOCS)光學模擬架構成為我們的快速空間成像(Aerial Image)模擬方法。我們將前像(Preimage)予以切割成為許多的次前像(Sub-Preimage),再對個別之次前像作多項式逼近而產生PPAP檔案。這些PPAP檔案可以在需要做空間成像模擬之時,以代入數值的方式快速求得微影熱點區域內之積分結果。比起傳統儲存整個空間成像的方法,我們的方法可以節省數十到數百倍的儲存空間,而運算時間並不會增加。 我們發現在使用了適當的模擬參數後,對於佈局上的一個金屬形(Metal Shape)予以移動或延長而造成微影熱點區域的空間成像的改變量,在OPC前後兩個不同方案下有著高度相關的情形,其相關係數可以高至0.88。此發現成為我們在OPC前以光學模擬為基礎計算自動修正方法的理論基礎。對於任一個微影熱點周邊一定範圍之內的所有可移動的金屬形,我們計算每一個金屬形的最佳移動量,並且稱之為修正動作(Fix Action)。此最佳移動量即是在DRC與LVS的限制之下,最佳化微影熱點區域內的OPC前之光學強度值之移動量。對於某微影熱點,我們選取其所有的修正動作集合的一個子集合,稱為修正導引(Fix Guidance)。修正導引的選取方式是在繞線器的一些限制之下,基於一個在微影熱點區域內,最佳化光學強度的貪婪試探法(Greedy Heuristic)。 我們將此修正動作及修正導引的產生法與一個業界的微影熱點偵測工具結合而創造了一個後繞線優化之光學模擬微影熱點自動修正流程(OSELF)。我們在幾個65奈米的業界真實設計上實驗了OSELF,與業界的只使用區域修正的軟體相比,OSELF達到了1.4-1.9倍的修正率,而使用了接近的執行時間。我們量測了電路的時脈延遲並發現到不管是業界軟體或是OSELF,做了修正之後的TNS與WNS的變動量均小到可以忽略。藉由結合以設計法則對於修正動作的調整,我們可以確保做完OSELF之後的整個設計不會有任何新增加出來違反DRC的區域。 我們也將OSELF演算法與繞線器中的拔起及再繞線(Rip-up & Reroute)的引擎結合創作了一個的統合修正流程。比起業界所使用的結合再繞線與區域修正的混合流程,我們的統合修正流程執行效率上有1.7-2.9倍的增進,且對於電路時脈的影響程度僅為業界混合流程的45-55%。此兩種修正流程在我們所測試的所有65奈米的真實設計上都有100%的修正率。

並列摘要


One of the most challenging parts in IC manufacturing of 65nm and below technology nodes is the lithography and Optical Proximity Correction (OPC) related part. For the 90nm and above process nodes, OPC and design rules embedded in a router are used to generate a manufacturing-friendly layout. However, for the 65nm and below process nodes, OPC and design rules are not sufficient to generate a manufacturing-friendly design in a reasonable turnaround time due to design complexity and the continuing usage of 193nm light source. Thus, lithography hotspot detection and fixing are now widely used in the post-route optimization stage to fix the layout defects that are unable to be addressed by OPC and design rules. The generation of fix guidance is an unresolved issue and geometrical matching methods are now used in commercial tools. However, the geometrical matching method needs to generate a large table by experiments and then store it as a database. This is a time consuming work, and the generated fix guidance will have poor yield in fixing the litho hotspots. In this thesis, an optical-simulation based lithography hotspot fix guidance generator and an automatic hotspot fix flow are proposed. We develop our aerial image simulation engine by enhancing the traditional Sum-Of Coherence System (SOCS) method. We divide the preimages into sub-preimages and apply polynomial approximations to generate the Preimage Polynomial Approximation Parameter (PPAP) file. The PPAP file can then be used to calculate the integration of the aerial image intensity of a hotspot area. Compared with lookup table, using of PPAP file can reduce the storage by 1-2 orders and also have similar run time. Subject to the shape changes, a strong correlation between the aerial image intensity difference maps of pre-OPC and post-OPC schemes is found. We experimented for different light sources and chose the light source with the best correlation coefficient value 0.88 as the parameter to our aerial image simulation engine. From this observation, we collect near a litho hotspot in a pre-OPC layout some fix actions that are local shape changes to optimize the optical intensity. A fix action is a single shape change that optimizes the optical gain in the hotspot area, subject to the Design Rule Check (DRC) and Layout versus Schematic (LVS) constraints. Then, fix guidances will be selected from the collected fix actions by a heuristic algorithm and input to a router for fixing the hotspot. The heuristic is a greedy heuristic which tries to optimize the optical gain in the hotspot area, subject to some constraint that is imposed by the router. We integrate the fix guidance generation method with a commercial lithography hotspot detection tool to create an automatic post-route Optical-Simulation-Embedded Local Fix (OSELF) flow that has been tested with industry 65nm designs. Compared with the commercial flow that uses only local fix, our method has a 1.4x-1.9x fix rate and spends similar run time. The circuit timing impacts in terms of Total Negative Slack (TNS) and Worst Negative Slack (WNS) values are negligible in both our proposed flow and the commercial flow. By integrating a DRC tailoring method during fix action generation, our litho hotspot fixing flow will not introduce any new DRC violation. We also combine our OSELF algorithm with a rip-up & reroute engine, and test on the same 65nm industry designs. Compared to the commercial tool that uses a hybrid (local fix plus reroute) fix flow, our combined flow runs 1.7x-2.9x faster, and the circuit timing impact of our flow is only 45-55% of that of commercial flow. Both our combined flow and the commercial hybrid flow achieve a 100% hotspot fix rate.

參考文獻


[1] M. Mark, “DFM EDA Technology: A Lithographic Perspective,” in Proc. IEEE Symposium on VLSI Technology, pp. 90–91, June 2007.
[2] K. Jain, M. Zemel, and M. Klosner, “Large-Area, High Resolution Lithography and Photoablation Systems for Microelectronics and Optoelectronics Fabrication,” Proceedings of IEEE, vol. 90, no. 10, pp. 1681-1688, October 2002.
[7] J. Mitra, P. Yu and D.-Z. Pan, “RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations,” in Proc. Design Automatic Conference, pp. 369-372, Anaheim, CA, June 2005.
[8] F. Schellenberg, “A Little Light Magic,” IEEE Spectrum, vol. 40, no. 9, pp. 34-39. Sep. 2003.
[9] Y. C. Pati, A.A. Ghazanfarian, and R.F. Pease, “Exploiting Structure in Fast Aerial Image Computation for IC Patterns,” IEEE Transactions on Semiconductor Manufacturing, vol.10, no.1, pp. 62-74, Feb. 1997.

延伸閱讀