減少自動化設計除錯中誤認的錯誤根源

Error Candidate Reduction in Automated Design Debugging

尹煜帆(Yu-Fan Yin)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.00317

摘要

功能性驗證可以對於一個有錯誤的設計，找出一條錯誤軌跡，其中包含了設計的規格與實作之間的不一致處。而自動化設計除錯可以利用這條錯誤軌跡，找出可能導致此錯誤的根源。這方面過去已經有許多能快速處理大型設計與長軌跡的研究，但是所找出的錯誤根源品質卻仍然不足，造成設計者要用人工的方式從幾百到幾千個可能的錯誤根源中，找出真正的錯誤根源。這篇論文提出了一個二級的除錯架構來減少誤認的錯誤根源。第一級使用了傳統的除錯演算法找出初始的錯誤根源。在第二級中，我們利用注入錯誤、狀態選擇，以及使每次找到的錯誤傳送路徑有所不同等技術，來產生替代的測試輸入。然後替代的測試輸入會被驗證並用來產生新的錯誤軌跡。利用此軌跡除錯後，如果有錯誤根源不在原本的可能的錯誤根源及新得到的可能的錯誤根源的交集中，那這些被誤認的錯誤根源即可被移除。實驗結果顯示我們所提出的演算法可以減少超過75%可能的錯誤根源，顯示出此方法用於改善設計除錯技術的可行性。

關鍵字

除錯 ； 診斷 ； 驗證

並列摘要

Given an erroneous design, functional verification returns an error trace containing a mismatch between the specification and the implementation of a design. Automated design debugging utilizes this error trace to identify candidates causing the error. There are remarkable debugging works in handling large designs and long error traces. However, the quality of error candidates remains poor, and it’s hard for designers to locate the actual error source among hundreds or thousands of candidates. This thesis proposes a two-stage debugging framework that reduces error candidate number. The first stage performs conventional debugging algorithm to get initial error candidates. In the second stage, alternative test sequences are generated by error injection, state selection, and error propagation path differentiation techniques. Then, the alternative test sequences are validated to produce alternative error traces. After debugging, redundant candidates can be removed if they are not in the intersection of the original candidate set and the new candidate set. Experimental results show that the proposed algorithm is able to reduce more than 75% error candidates, which demonstrates the viability of this approach in improving design debugging techniques.

並列關鍵字

debugging ； diagnosis ； verification

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