排程方法之處理器成本最佳化效能評估

在現今的軟硬體共同設計領域中，存在著很多由前人所設計與構想的演算法以求用電子計算機來協助嵌入式產品的設計者快速地將腦中的構想與軟體的需求，能夠搭配上適合的硬體架構來完成實體的產品。這種由電腦輔助的設計工具在近代的軟硬體共同設計頗為普遍，然而過去的設計方法都是各自一片天的狀況，尚未有研究者深入與系統性地剖析與比較這些方法，以求能找出最適化的演算法組合來產生最佳化的處理器硬體成本。但是，成本與所謂的設計-上市時間，都是考驗一個產品的競爭力的指標，因此藉由實驗的分析與探討，我們試圖解析相關的影響因素，並且討論了如何使處理器的成本最佳化的最佳策略選擇。

關鍵字

排程；處理器；最佳化；成本；效能評估；評估

並列摘要

The optimization problem of processor cost in hardware/software co-synthesis is highly challenging in embedded system designs. In this paper, we address co-synthesis issues in heterogeneous cores, communication overheads, and task dependency. In particular, different co-synthesis strategies are investigated with respect to the processor allocation, task assignment, and task scheduling. Evaluation of various combinations of strategies is explored to derive insights for hardware/software co-synthesis. The needs of multiple cores are driven by many emerging application domains, such as video encoding/decoding, wireless communication, and interactive interface. It has become very popular for embedded systems to have multiple heterogeneous cores, where cores are interconnected by various types of communication links. One important challenging problem confronted by many system designers is how to rapidly prototype application-specific embedded system architectures with integration considerations of different combinations of software and hardware, provided that various constraints on real-time performance, reliability, and cost remain satisfied. How to minimize the architecture cost and to satisfy applications' constraints presents tremendous challenges in the optimization problem of embedded systems.

並列關鍵字

scheduling ； processor ； cost ； evaluation ； cosynthesis

參考文獻

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for allocating task graphs to multiprocessors,” IEEE Transactions of Parallel

co-synthesis for embedded systems,” Journal of VLSI and Signal Processing,

[5] RadoslawCzarnecki and Stanislaw Deniziak, “Resource constrained co-synthesis

of self-reconfigurable sopcs,” International Workshop on Design and Diagnostics of

國際替代計量

排程方法之處理器成本最佳化效能評估

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