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  • 學位論文

射頻辨識系統掃讀器發射模組及電子標籤基頻電路設計

Design of Reader Transmitter and Tag Baseband Circuit for Radio-Frequency Identification

指導教授 : 江簡富

摘要


本論文提出一個操作在2.45 GHz的射頻辨識系統(RFID)發射器模組之設計,且以FR4電路板驗證。編碼器輸出的基頻信號切換以Gilbert-cell架構為基礎的混波器,改變本地震盪器(LO)的訊號路徑以產生振幅鍵移調變(ASK)的射頻信號。此架構簡化數位類比轉換器的設計。此發射器在5 V電源供應下約消耗483 mW的功率,其中混波器消耗約289 mW。功率放大器在2.45 GHz操作下可提供13.5 dB的功率增益,且輸出端的電壓駐波比約為1.35。 本論文另提出無碰撞的被動式電子標籤基頻電路設計,且以FPGA實現。此架構僅需要nTb辨識一n-bit的電子標籤,同時需要(16m+n+13)Tb將m個字元(word)的資料回傳至掃讀器。其時脈產生器以數位電路實現,取代傳統式的震盪器,藉以提升頻率的精確度。

並列摘要


A 2.45 GHz RFID transmitter module has been designed and verified using FR4 printed circuit board. The mixer is designed using Gilbert-cell-based differential pair to switch the LO signal path from the baseband signal of encoder to generate the ASK RF signal at the output of mixer. It simplifies the circuit design of D/A converter. The data rate can be up to 150 kbps at typical range of 10 m under the raw-data bit error rate of 10−3. The transmitter consumes 483 mW of power at 5 V supply voltage, of which only 289 mW is consumed by the mixer. The amplifier has the power gain of 13.5 dB at 2.45 GHz, and the VSWR at the output port is 1.35. A collision-free baseband circuit of passive RFID tag is designed and implemented in FPGA. It takes only about nTb to identify a single tag of n bits, and of about (16m+n+13)Tb to respond to the reader m words of data. The digital clock generator is used instead of conventional oscillators to improve frequncy accuracy.

參考文獻


“A single-chip CMOS transceiver for UHF mobile RFID reader,” IEEE Int. Solid-State
[3] S. Zheng, F. Yu, and Y. Zhu, “A novel RFID transceiver architecture with enhanced
2077, Sep. 2007.
Jan. 2005.
Ajjikuttira, W. G. Yeoh, and R. Singh, “An 860 to 960MHz RFID reader IC in CMOS,”

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