NAND型快閃記憶體上之NOR型快閃記憶體的模擬策略

快閃記憶體大致可分為兩類：NOR型快閃記憶體及NAND型快閃記憶體。一般而言，因為有就地執行（eXecute-In-Place，XIP）和快速讀取等特性，NOR型快閃記憶體應用上適用於儲存程式的可執行檔。而擁有較大容量與較快寫入速度的NAND型快閃記憶體則適用於資料儲存。此外，兩者在成本上有很大的差距，NOR型快閃記憶體相對於NAND型快閃記憶體高出許多。基於市場的趨勢，若能以較具經濟效益的NAND型快閃記憶體取代NOR型快閃，將可大幅地降低成本、提升毛利。在這篇論文中，我們於既有的NAND型快閃記憶體中加上一層靜態隨機存取記憶體（SRAM）當作快取，它提供了隨機存取的能力以及較快的存取速度。我們提出了一種預測方法，經由充分地對特定應用程式之存取軌跡的觀察與分析，系統會記憶應用程式的存取行為，讓資料在被實際讀取之前就被傳入快取中。藉著這樣的學習機制能，系統能準確地將執行時所需的資料預先載入，使資料總是在快取中被讀取。因為在嵌入式系統上，資源是很有限的，技術的關鍵在於如何以最少的硬體資源支援預測的資訊。為避免花費額外的記憶體空間，我們利用了NAND型快閃記憶體中的保留區（spare area）來存放預測資訊。論文的最後透過一系列的實驗印證了所提的方法確實可達到高效率且低成本的快閃記憶體管理，我們有效地降低了資料在快取中失誤的可能，進而提升系統的整體效能。特別是針對某些存取模式固定的應用程式，僅須使用極少量的快取便可讓效能有可觀的改善。

關鍵字

NAND型； NOR型；快閃記憶體；資料快取

並列摘要

This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of applications. An implementation strategy is proposed in the storage of the prefetching information with limited SRAM and run-time overheads. An efficient prediction procedure is presented based on information extracted from application executions to reduce the performance gap between NAND flash memory and NOR flash memory in reads. With the behavior of a target application extracted from a set of collected traces, we show that data access over NOR flash memory is responded effectively over SRAM that serves as a cache for NAND flash memory.

並列關鍵字

NAND ； NOR ； flash memory ； data caching

參考文獻

[10] L.-P. Chang and T.-W. Kuo, "An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems," in IEEE Real-Time and Embedded Technology and Applications Symposium, 2002, pp. 187-196.

[11]

[13] C.-H. Wu and T.-W. Kuo, "An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems," in IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 2006.

[15] K. S. Yim, H. Bahn, and K. Koh, "A Flash Compression Layer for SmartMedia Card Systems," IEEE Transactions on Consumer Electronics, vol. 50, no. 1, pp. 192-197, Feburary 2004.

[21] F. Douglis, P. Krishnan, and B. Marsh, "Thwarting the power-hungry disk," in Proceedings of the 1994 Winter USENIX Conference, 1994, pp. 292-306. [Online]. Available: citeseer.ist.psu.edu/douglis94thwarting.html

國際替代計量

NAND型快閃記憶體上之NOR型快閃記憶體的模擬策略

全文下載

主題瀏覽