伸張應力對超薄閘極氧化層金氧半電容元件之影響

Effect of Tensile Stress on MOS Capacitors with Ultra-thin Gate Oxide

陳星霖(Hsing-Lin Chen)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.10068

摘要

近年來，由於半導體技術的進步，金氧半元件在尺寸上的縮小化，有著顯著的成果。根據國際半導體技術藍圖（ITRS）的預測，西元2012年時，元件上的等效氧化層厚度將會達到0.5奈米，此時的矽氧化層因為太薄而易產生大量漏電流，影響元件上的電特性，進而產生穩定度的問題。由於氧化層的特性在超大型積體電路元件的表現及可靠度上扮演著極為關鍵的角色，因此，在高介電質材料做為元件絕緣層的相關問題尚未解決之前，如何提升二氧化矽介電層的品質仍是目前非常重要的課題。在本篇論文中，我們提出一個用機械應力彎曲矽晶圓的方式，使矽晶格產生應變，並將此伸張應力分別應用在成長二氧化矽氧化層時及金氧半元件製程之後，並且利用傾斜陰極之陽極氧化系統生長不同厚度之氧化層，探討此機械應力對其電特性及穩定性的影響。實驗結果證明，無論是張力成長之氧化層技術或伸張形變溫度施壓技術，都能增進金氧半元件的氧化層品質。另外，我們在最後對此技術提出未來的研究方向。

關鍵字

伸張應力 ； 超薄閘極氧化層 ； 金氧半電容元件

並列摘要

In recent years, due to the advanced technology of semiconductor, there are great results in the scaling of MOS devices. Based on the International Technology Roadmap for Semiconductors (ITRS), the equivalent oxide thickness (EOT) should be 0.5 nm in 2012 and high gate leakage current will be produced because the thickness of oxides becomes thinner. The leakage current will make the device lose its electrical characteristics and cause reliability problems. The quality of oxide plays a critical role to the device performance and reliability of ultra-large scale integrated circuits. Therefore, it is still an important topic to promote the quality of silicon-dioxide dielectrics before the problems of high-κ gate dielectric be solved. In this thesis, the strained silicon concept by applying mechanical tensile stress on silicon was proposed. The tensile stress is applied on oxidation and after sample preparation, separately. The electrical characteristics and reliability of different thick oxides prepared by tilted cathode anodization system will be discussed. From the experimental results, the quality of MOS gate oxides would be improved by either tensile-stress oxidation or strain-temperature stress. Finally, conclusions and some other suggestions for future work about this thesis were given.

並列關鍵字

Effect of Tensile Stress ； MOS Capacitors ； Ultra-thin Gate Oxide

參考文獻

[2] Jack S.Kilby, “Semiconductor Device-and-Lead Structure, July 30, 1959,” U.S. Patent 2918877, April 25, 1961.

[4] International Technology Roadmap for Semiconductors (ITRS), 2007 Edition.

[6] C. H. Choi, Y. Wu, J.S. Goo, Z. Yu, and R. W. Dutton, “Capacitance reconstruction from measured C-V in high leakage, nitride/oxide, MOS,” IEEE Trans. Electron Devices, vol.47, pp.1843-1850,2000.

[7] A. Nara, N. Yasuda, H. Satake, and A. Toriumi, “Applicability Limits of the Two-frequency Capacitance Measurement Technique for the Thickness Extraction of Ultrathin Gate Oxide,” IEEE Trans. On Semicon. Manufacturing, Vol. 15, pp. 209-213, 2002.

[8] K. J. Yang and C. Hu, “MOS capacitance measurements for high-leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, 1999.