寬操作區域之靜態隨機存取記憶體設計

Design of Wide-Range Static Random Access Memory

蘇翊傑(I-Chieh Su)

指導教授 ： 劉宗德

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800465

摘要

因為無線裝置與穿戴式裝置的廣泛運用及普及，低功耗的電路與系統設計變成一個重要的考量。此外，在未來的物聯網裝置之功率消耗也需要盡量壓低，低操作電壓是一個能讓我們達成低功率消耗和能源效率最直觀的方法。
在本論文中，我們實現一個能操作在0.25V(次臨界電壓區)到1V之寬操作電壓靜態隨機存取憶體，我們採用了八電晶體的單元架構獨立出讀取路徑與負電壓資料位元線作為改善寫入操作的輔助電路。這個單元架構與輔助電路是一個對於正確的操作於次臨界電壓區很好的組合。但是，這兩個方法還是有一些缺點。我們提出讀取路徑負向增壓，透過再利用負電壓資料位元線的增壓電路改善漏電流與主動電流的比例，以及只對選取的行作充電以減少增壓電路上電容的尺寸及功率消耗。在實施了讀取路徑反向增壓與選擇式資料位元線充電後，我們可以得到與普遍使用8T單元的靜態隨機存取記憶體相比，最小操作電壓降低100mV，可以在0.25V下正確的操作。

關鍵字

靜態隨機存取記憶體 ； 次臨界操作電壓 ； 低操作電壓 ； 低功耗 ； 讀寫輔助電路 ； 八電晶體單元靜態隨機存取記憶體

並列摘要

Low power circuit and system design is an important topic because of widespread wireless and wearable devices. Besides, the power consumption of future IoT devices must be as low as possible. Low operating voltage is one of the most effective ways which can help achieve low power consumption and high energy efficiency.
In this thesis, we realized a low-voltage SRAM which can operate at 0.25V (sub-threshold region) to 1V in TSMC 28nm technology. We employed 8T cell and used negative bit-line as write assist circuit. We proposed negative boost on the read path to improve read Ioff/Ion ratio by reusing boosting circuit of the negative bit-line, and selectively charged SRAM bit line to further decrease power consumption and boosting capacitor size. Using read-path negative boosting and selective bit-line charging, our work achieves a 100mV reduction in the minimum operating voltage and can operate correctly down to 0.25V compared with the 8T cell SRAM.

並列關鍵字

SRAM ； sub-threshold voltage ； low operating voltage ； low-power ； read and write assist ； 8T-bitcell SRAM

參考文獻

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