一個10.5Gbps可適性時域決策回授等化器

A 10.5Gbps Adaptive Time-Based Decision Feedback Equalizer

彭馨儀(Hsin-Yi Peng)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200363

摘要

現今，傳輸通道的有限頻寬導致傳輸訊號失真，使位元錯誤率升高，為了解決此問題，等化器被廣泛的使用，但隨著製程的進步，電源電壓逐漸下降，等化器的運算電路在設計上變得更困難，因此，將使用時域架構來避免此狀況。此外，通道衰減的特性會隨通道材質及長度的不同而改變，因此，自動調整係數對於等化器是有需求的。

本論文提出一個有時間偏差校正功能之10.5Gbps可適性2-tap時域決策回授等化器，實作於40奈米製程中，採用SSLMS演算法來實現可適性，根據量測結果:時域決策回授等化器可適當的補償小於14.5dB衰減的串列資料，其中，等化器的面積為126um × 110um，等化器的功率為10.3mW。

關鍵字

時域 ； 適應性演算法 ； 決策回授等化器 ； 高速接收器 ； 時間偏差校正

並列摘要

Nowadays, the aggregate bandwidth of the data traffic is strictly limited by the channel characteristics. The limited bandwidth of the channel will deteriorate the bit error rate performance. Thus, the equalization becomes more and more important in the wireline systems. Moreover, the channel attenuation greatly varies with materials and lengths, and hence the adaptation techniques for the equalizer are required.

This work is a 10.5Gbps adaptive 2-tap time-based decision feedback equalizer with offset calibration technique. It is fabricated in 40nm CMOS technology. Using SSLMS algorithm to adjust coefficient. From the measurement result, this equalizer can well compensate the channel loss under 14.5dB attenuation. The chip area of equalizer is 126um × 110um. The power consumption of equalizer only is 10.3mW.

並列關鍵字

time-based ； adaptive ； decision feedback equalizer ； high speed transceiver ； offset calibration

參考文獻

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