基於數位時間轉換器輔助時間數位轉換器之小數型全數位鎖相迴路

A Fractional-N DTC-Assisted TDC-Based All-Digital Phase-Locked Loop

林淳濂(Chun-Lien Lin)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200396

摘要

在無線通信和物聯網系統中，頻率合成器是不可或缺的組件，需要提供低功耗和低雜訊的精準頻率。在傳統解決方案中，類比鎖相迴路被廣泛地應用，然而，隨著製程技術的演進，全數位鎖相迴路因其小面積、低功耗、高度整合、高可重構性和可應用各種校正的能力等數位化實現的特點而逐漸受到越來越多的關注。
本論文實現一個低功耗和低均方根抖動量的小數型全數位鎖相迴路，通過降低時間數位轉換器所需偵測範圍的數位時間轉換器輔助時間數位轉換器組合，和降低時間數位轉換器操作頻率的閘控電路，大幅改善了功耗。提出的時間窗自適應步長數位時間轉換器增益最小均方根校正以適當的硬體成本提供更佳的穩定性。本作品採用TSMC 90奈米製程設計，模擬的均方根抖動量為692 fs，功耗為1.15 mW，FoMJitter為-242.5dB。

關鍵字

全數位鎖相迴路 ； 數位時間轉換器 ； 時間數位轉換器 ； 數位時間轉換器增益校正

並列摘要

In wireless communications and Internet-of-Things (IoT) systems, frequency synthesizers are indispensable components which are required to generate accurate frequency with low power and low noise. In conventional solution, analog PLLs are widely adopted. However, as technology scaling, all-digital PLLs have gained more attention for benefiting from digital intensive nature such as low area, low power, high integration, high reconfigurability and capability of various calibration.
In this thesis, a low-power and low-jitter fractional-N ADPLL is presented. The power consumption is significantly improved by a DTC-assisted TDC combination which reduces the required TDC detection range. Furthermore, a gating circuit is implemented to decrease the TDC operating frequency. The proposed adaptive-step-size time-window DTC gain LMS calibration provides better stability with adequate cost. The overall ADPLL is designed in TSMC 90-nm CMOS process. The simulated integrated jitter is 692 fs with power consumption of 1.15 mW and the corresponding FoMJitter is -242.5 dB.

並列關鍵字

ALL-Digital Phased-Locked Loop ； Digital-to-Time Converter ； Time-to-Digital Converter ； DTC Gain Calibration

參考文獻

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