透過您的圖書館登入
IP:3.17.173.138
  • 學位論文

第一原理新穎通道與鐵電材料研究及後端依時性介電崩潰之可靠度模型

First-Principle Calculation of Novel Channel and Ferroelectric Materials with additional BEOL TDDB Reliability Modeling

指導教授 : 劉致為
本文將於2024/08/16開放下載。若您希望在開放下載時收到通知,可將文章加入收藏

摘要


在本篇論文中著重於以第一原理進行藍絲黛爾結構鍺以及氧化鉿基鐵電材料之特性分析。此外,亦會探討低介電係數介電材料於後段製程線路之介質崩潰以及可靠度分析。 當電晶體尺寸持續微縮後,使用具有高遷移率的通道材料來增加驅動電流或降低能耗是未來半導體元件發展的方向之一,為了追求高效能的通道表現,使用新穎之材料如三五族半導體是一可嘗試的方法,或者使用相同材料但不同結構之主流製程材料達成高遷移率同時降低成本。在論文的第一部分將會針對鍺之同素異形體,藍絲黛爾鍺進行特性分析,包含其能帶結構、等效質量、彈道電流以及應變響應等皆會詳細分析。具有穩定結構之藍絲黛爾鍺預期能有效提升元件表現而不改變其材料構成,而其直接能隙之特性亦利於用於光電元件之應用。 在提升元件表現特性的同時,降低其能耗亦是極為重要的一環。在不降低元件的驅動電流以及操作頻率的前提下,降低元件的操作電壓為降低其操作功率的有效手段。在設計上,元件之截止電流須保持相同或者更低以保持低靜態功率,與此同時,亦須保持高的操作電流,因此,盡可能降低元件之次臨界擺幅十分重要。然而,傳統電晶體的次臨界擺幅在室溫時有著60 mV/dec 的極值限制,需要使用其他方法使其次臨界擺幅能進一步降低。負電容電晶體為一有效克服傳統次臨界擺幅極限值之方法。加入鐵電材料到閘極堆疊的負電容場效應電晶體,其利用鐵電材料內之偶極矩隨偏壓改變時改變極化方向之特性,將能使次臨界擺幅小於60 mV/dec。由於鐵電材料主要是藉由外加電場來改變極化方向,其主要操作方式為利用電極化方向與外加電場的關係,因此鐵電材料內之偶極矩隨著外加電場頻率不同而產生的變化十分重要。在論文的第二部分,將以第一原理進行正交結構氧化鋯鉿之特性分析,利用其能量與極化之關係確定其鐵電特性。以及,利用分子動力學模型計算其動態反應。除此之外,亦會探討應變對其造成之影響。 最後,在元件尺寸不斷微縮的過程中,其失效機制亦是十分重要的一環,故在此論文中亦會探討後段製程中介電層的崩潰機制,造成介電層崩潰的原因可能為施加電場或是漏電流造成,如何精確的了解其機制並藉此預測其可靠度變化是十分重要的。藉由後段製程中介電層之漏電流以及時依性介電層崩潰之數據,建立可靠度的模型,藉以進行元件於正常使用狀態下之可靠度預測。

並列摘要


In this dissertation, the characteristic of lonsdaleite germanium as the novel channel material and hafnia-based ferroelectric material are investigated. Besides, the failure model of the low-k dielectrics in the back-end-of-line is also discussed. As the device keeps scaling down, the high mobility channels are proposed to enhance drive current and reduce power consumption. To pursue high performance channels, new material such as III-V semiconductor is one way to explore. Alternatively, the same material with an optimum crystalline structure is more cost-effective to obtain high mobility. In the first part of this dissertation, lonsdaleite Ge, the allotrope of diamond structure Ge is discussed including the bandstructure, effective mass, ballistic current and strain response. The stable lonsdaleite Ge has the potential to enhance the performance of n-channel FETs without introducing new materials. The direct-bandgap characteristic also makes lonsdaleite Ge potentially useful for photonic applications. When the performance of devices enhances, it is also important to reduce the static power consumption. Transistor operating frequency and capacitance cannot be lowered in pursuit of higher speed and on current. Therefore, lowering VDD is the solution to reduce the dynamic switching power as technology node progress. In the transistor design, IOFF should remain the same or become even lower to maintain the low static power (IOFFVDD), and ION should become larger for decreasing VDD. As a result, devices with steep subthreshold slope (SS) are desired. However, SS of the traditional transistor is limited at 60 mV/decade at room temperature due to the thermionic emission transport mechanism. Negative capacitance FET (NCFET) is a method to overcome the limited SS. Ferroelectric material can be used to amplify the gate voltage by the internal polarization of it. A capacitor made with such a ferroelectric material can exhibit “negative capacitance,” where the stored charge in a stable state is negative with respect to the applied voltage. Such negative capacitance can be exploited for “voltage amplification”. This voltage amplification can be exploited in the gate-stack of a transistor in order to achieve SS < 60 mV/decade without changing the transport physics of the FET. However, it remains challenging whether the operation speed of NCFETs is applicable for high-speed circuit. Therefore, the research of the transient behavior of ferroelectric is important for the development of NCFET. In the second part of this dissertation, the characteristic of the HfO2 ferroelectric material with different Zr content is calculated by first principle. And the dynamic polarization with time is calculated based on density functional theory (DFT) and molecular dynamic model. The metastable life time of HfZrO2 is smaller than 0.2 ps, which has potential of high-speed operation for device applications. In addition, the strain response of HfO2 is also discussed. Finally, the breakdown mechanism of the back-end-of-line (BEOL) dielectric is investigated since it has become an important failure mechanism with the reduction of device dimensions. Several models of the breakdown process have been proposed, with the mechanisms being broadly classified as being dependent on the dielectric electric field, or the leakage current through the dielectric under a voltage bias. The most pressing issue to be resolved for accurate reliability estimation of BEOL dielectrics is the field dependence of the breakdown mechanism. By combining modeling of the leakage current of BEOL capacitors with time dependent dielectric breakdown (TDDB) data, we show that the hard breakdown of capacitors during electrical stress is related to the leakage current flowing through the dielectric. Moreover, we find the breakdown occurs after a critical energy density has been dissipated in the dielectric.

參考文獻


Chpater 1
[1] Gordon E. Moore “Cramming more components onto integrated circuits,” IEEE Solid-State Circuits Society Newsletter, Vol.11, Iss, 3, 2006.
[2] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry, “A 22nm high performance and lowpower CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in Proc. Symposium on VLSI Technology, June 2012, pp. 131-132.
[3] Christianto C. Liu, Shuo-Mao Chen, Feng-Wei Kuo, Huan-Neng Chen, En-Hsiang Yeh, Cheng-Chieh Hsieh, Li-Hsien Huang, Ming-Yen Chiu, John Yeh, Tsung-Shu Lin, Tzu-Jin Yeh, Shang-Yun Hou, Jui-Pin Hung, Jing-Cheng Lin, Chewn-Pu Jou, Chuei-Tang Wang, Shin-Puu Jeng, Douglas C.H. Yu, “High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,” in IEEE IEDM Tech. Dig., Dec. 2012, pp. 14.1.1-14.1.4.
[4] Mark T. Bohr, Ian A. Young, “CMOS Scaling Trends and Beyond,” IEEE Micro, Vol. 37, Iss. 6, 2017.

延伸閱讀