- 學位論文
高效率視訊編碼標準非除區塊濾波器編碼器之分析及積體電路架構設計
Analysis and VLSI Architecture Design of Non-Deblocking Loop Filter in HEVC Encoder
摘要
在人類視覺感知系統的歷史裡，先進的視訊應用是具有劃時代意義的影響。這些電視技術的應用走向更豐富多彩以及更高的畫素。為了追求更高的視覺品質和更逼真的視覺感受，越來越多的先進視訊應用正在開發，如高解析度電視（HDTV），3D應用以及網絡視訊串流。然而在視訊應用中，巨大的數據資料大小和數據遺失為兩大重要的挑戰。為了解決這兩大挑戰，視訊編碼變得越來越重要。隨著對於更高品質以及更高解析度的視訊應用、頻寬的限制以及視訊壓縮技術的進步，下一代的視訊編碼標準，高效率視訊編碼標準(HEVC)也正在如火如荼的制訂中，其目標是相比於H.264/AVC再進一步降低50%的壓縮效率。在高效率視訊編碼標準中，很多新的編碼技巧被提出，在本篇論文中，我分析其中的非除區塊濾波器編碼器的演算法並針對其演算法設計及實作其積體電路架構。 非除區塊濾波器的目的在於減少原圖與壓縮圖之間的誤差。在非除區塊濾波器中有兩種新採用的壓縮工具，為可調式樣本補償以及可調式迴路濾波器。非除區塊濾波器提供了5%的壓縮效率進步，但付出的代價是極高的演算複雜度；此外現在的非除區塊濾波器演算法並不適合於硬體的實作。為了將非除區塊濾波器實作在硬體上並降低演算複雜度，我提出了許多技巧以及硬體架構。首先，我針對非除區塊濾波器的演算法做了許多化減，結果顯示大多數的硬體資源可以被節省同時維持住壓縮效率以及壓縮品質。再來我提出了統一非除區塊濾波器流程、兩級非除區塊濾波器硬體架構以及LCU level-D資料重覆利用技巧，並應用這些方法實作於硬體上。基於我們所做的分析、演算法的化減與改進以及硬體架構的設計，我所提出的硬體架構減少了75%頻寬使用、99%的內部記憶體使用以及超過40%的硬體運算資源，同時只降低了1.29%的壓縮效率。此為全球第一的高效率視訊編碼標準非除區塊濾波器編碼器的硬體實作，規格為7680x4320序列，每秒30幀，每秒處理能力為1.49億個像素。
並列摘要
Advanced video applications have an epochal impacts to the history of human visual perception system. Television and communication technology evolve toward more realistic and higher resolution. Many applications, such as high definition TV (HDTV), 3D device and Internet video streaming are developed to fulfill the human desire. However, the massive data size and data loss are still the challenges for these applications. With the advances in video coding technology, the demand of high quality and high definition video encourages the development of next generation video coding standard, High Efficiency Video Coding (HEVC). In 2010, ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) formed a Joint Collaborative Team on Video Coding (JCT-VC) and has began working on the next generation video coding standard HEVC. Many advanced techniques and enhanced coding tools are proposed in HEVC. In this thesis, we analyze and design the algorithm and hardware architecture of non-deblocking loop filter in HEVC. The non-deblocking loop filter aims to decrease the distortion between original pictures and reconstructed pixels. Sample adaptive offset and adaptive loop filter are two newly adopted tools in HEVC. The non-deblocking loop filter has 5\% coding efficiency gain; nevertheless, the cost is high complexity. In addition, the algorithm of non-deblocking loop filter is not hardware friendly. In order to implement the non-deblocking loop filter on hardware and reduce the complexity, we propose many techniques and hardware architecture. First, we propose many simplifications on SAO and ALF, especially on ALF. We show that much of the hardware resource can be saved yet keeps the video quality and coding performance. Second, we propose unified non-deblocking loop filter flow, two-stage non-deblocking loop filter architecture and LCU level-D data reuse to implement the non-deblocking loop filter on hardware. The proposed hardware architecture reduces 75\% of external memory access bandwidth, 99.9\% of memory usage and more than 40\% of hardware computation resource with only 1.29\% of coding efficiency loss. Based on the proposed algorithm and hardware architecture design, a worldwide first non-deblocking loop filter of HEVC standard hardware with 1.49G pixels/s throughput under the specification Ultra-HD $7680 imes4320$, 30fps is achieved.