在非平面矽基板生長閘極氧化層之金氧半電容元件於反轉區之特性探討

Investigation of Inversion Characteristics of Non-planar MOS Structures

林黃玄(Huang-Hsuan Lin)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00750

摘要

本論文之研究主要在探討生長於非平面結構P型矽基板之金氧半電容元件於電性上與平面結構元件之間電性的差別並探討反轉區之電流特性。首先，在閘極施加正電壓的反轉區發現非平面結構的電流比平面結構的電流大上2到3個數量級，而且電流沒有像平面結構一樣的飽和特性。進一步分析可以發現非平面結構反轉區電流隨著氧化層厚度增加而有漸小的趨勢，而平面結構則相反。為了瞭解非平面結構電特性對於電流的影響，吾人使用Silvaco TCAD 模擬非平面結構的電場、電位以及少數載子於反轉區的分布情形，並進一步探討電流的分布。結果發現非平面結構的矽基板於凹入處電位梯度較平面處大，因此電場也較大，經由模擬也發現此處的電流較為大，此外再加上蝕刻所造成的矽基板表面的粗糙度使氧化層在生長時會有均勻度的問題，造成在大電場下容易有漏電流路徑形成。所以相對於平面結構，非平面結構多了此處的穿隧電流而使反轉電流大上許多。至於非平面結構其反轉電流不易飽和的原因則是由於在矽基板凸出處有少數載子聚集的現象，因此多了可以持續提供電子的區域使得電流較不易達到飽和。
接著，吾人藉著定電壓應力測試元件的穩定性中發現，平面結構隨著施予電壓應力的增加，其反轉區電流有先減而後增的現象。一開始的電流減少是因為施予一段時間的負電壓之後氧化層會有負電荷被抓陷於其中，當電極給予正偏壓時，由於屏蔽效應使得電洞的位障增加進而降低電流；隨後則是由於局部氧化層破壞而使電流隨電壓上升。非平面結構則由轉角處的非均勻氧化層的局部破壞主導，因此隨著應壓增大而電流隨之上升。此外，在計算介面陷阱密度後可以發現非平面結構的陷阱密度大於平面結構，且兩者皆會有隨應電壓增加而上升的現象。
在本論文中，非平面結構矽基板在反應式離子蝕刻之後另有一組予以濕式短暫蝕刻來減緩矽基板粗糙程度的元件，結果發現其電特性與沒經濕式蝕刻的元件相似，同樣具有不飽和的反轉區電流，但其反轉區電流小了將近一個數量級且介面陷阱密度也較小，顯示出短暫的濕式蝕刻可以增進非平面結構於轉角處氧化層均勻度與穩定度。另外，電子穿隧式顯微鏡影像亦顯示出經濕式蝕刻的確增進了氧化層的均勻性。

關鍵字

非平面 ； 二氧化矽 ； 電流電壓曲線 ； 電性模擬

並列摘要

This thesis studies the electrical differences between the p-type MOS devices fabricating on non-planar and planar silicon substrates. The current conduction mechanism of inversion region and oxide reliability are emphasized.
The I-V characteristics show that the non-planar device current in inversion region is 2 to 3 orders greater than the planar device, and unlike the planar device, the current is not saturated. Under the same positive bias, the inversion current of non-planar and planar devices have opposite dependency on the oxide thickness. The inversion current of planar device increases with oxide thickness and the non-planar is opposite. In order to understand the electrical property of non-planar structure, we use Silvaco TCAD software to simulate the distribution of energy potential, electric field and minority carrier concentration in non-planar structure. The simulation results reveals that the potential gradient of concave region of silicon surface is much greater than the planar region, which indicates large electric field existing around the concave region. In addition, owing to the non-uniformity of oxide grown on etched silicon, the leaky path is likely to form under large voltage bias. Therefore, both the tunneling current induced by large electric field and the leakage current induced by non-uniform oxide in the corner region contribute to much higher current compared to the planar device. Besides, the minority carrier crowding in the silicon convex region of non-planar device contributes to the continuous supply of minority carriers, which makes inversion current hard to saturate.
In constant voltage stress(CVS) reliability test, it is found that the inversion current of planar device decreases after low voltage stress and then increases after high voltage stress. The decreasing current after low voltage stress can be attributed to electron trapping, which increases hole barrier by shielding. However, when voltage stress further increases, the local oxide is weakened and leakage current increases. For non-planar device, the non-uniformity of corner oxide makes it easy to be broken under voltage stress, thus the inversion current increases with increased voltage stress. Besides, the extracted interface trap density from C-V curve shows that the trap density of non-planar device is much higher than planar device, and both of them increase with increasing voltage stress.
In this work, we prepare another non-planar device with short time wet etching after RIE process to smoothen the roughness of silicon surface. I-V characteristics shows that the inversion current is decreased by one order, and the trap density extracted from C-V curve is reduced comparing to non-planar device without wet etching. Therefore, it is shown that the oxide quality of non-planar can be improved by short wet etching after RIE process.

並列關鍵字

non-planar ； SiO2 ； I-V curve ； TCAD

參考文獻

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