毫米波除頻器及相移器之研究

Research on Millimeter-Wave Frequency Dividers and Phase Shifters

林毓軒(Yu-Hsuan Lin)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/博士(2018年)

https://doi.org/10.6342/NTU201800502

摘要

本論文主要分為兩部分，分別是毫米波寬頻除頻器和毫米波低相位移和振幅誤差之相移器。
第一部分是有關毫米波寬頻除頻器的研究。除頻器是鎖相迴路中的關鍵電路之一，在毫米波頻段的米勒除頻器(Miller frequency divider)和注入鎖定式除頻器(Injection-locked frequency divider)廣泛的被使用，然而和低頻率的除頻器相比頻寬受到相當大的限制，因此本論文提出兩個方法，用來改善兩種毫米波除頻器的頻寬。第一個除頻器是操作在60GHz且使用65奈米CMOS製程製作的米勒除頻器。此除頻器使用了弱反轉區(weak inversion region)偏壓的混頻器使其能達到57%的鎖定比例頻寬(35.7至64.2 GHz)，而且功耗僅1.6毫瓦。第二個除頻器是使用分裂式變壓器耦合振盪器(split transformer-coupled oscillator)的注入鎖定式除頻器。使用了此架構的注入鎖定式除頻器可以增加操作頻率和鎖定頻寬且不會增加額外晶片面積及功率消耗。此注入鎖定式除頻器在不需要額外調控機制下達到25.4%的鎖定比例頻寬(75.1至97 GHz)，且在0.7V供給電壓下有2.45毫瓦的功率消耗。
第二部分是有關應用在60GHz相位陣列的毫米波低相位移和振幅誤差之相移器設計。相移器為相位陣列(phased array)系統中的關鍵元件，本論文中，設計了一種低相位移和振幅誤差的四相位旋轉器由四相位產生器和相位選擇器所組成，用以搭配射頻(RF)端和本地振盪源(LO)端相移器，使這兩個相移器皆能達到360度的相移而且具有低相位移和振幅誤差的特性。射頻端相移器是基於開關式相移器所設計，是全被動的架構且達到四位元的數位式控制。此相移器最大均方根振幅誤差為0.5dB，最大的均方根相位誤差為5度。另一個本地震盪源端相移器使採用注入鎖定式架構，此相移器達最大震幅誤差為±0.3 dB，最大相為誤差為5度。具有-10 B dBm的輸出功率和18 毫瓦的功率消耗。

關鍵字

互補式金氧半場效電金體 ； 除頻器 ； 變壓器 ； 振盪器 ； 注入鎖定 ； 相移器

並列摘要

This dissertation consists of two main parts, the first part is design of wide band-width millimeter-wave (MMW) frequency divider, and the second part is about 60 GHz phase shifter with low phase and amplitude error.
In the first part, two MMW frequency dividers for MMW PLL are presented. The first frequency divider is 60 GHz Miller divider demonstrated in 65 nm CMOS. The Miller divider achieves 57% input locking range from 35.7 to 64.2 GHz with power consumption of 1.6 mW owing to using weak inversion bias mixer. The second fre-quency divider is a W-band injection-locked frequency divider (ILFD) fabricated in 90 nm CMOS, The STCO (split transformer-coupled oscillator) technique is proposed and utilized in ILFD and the operation frequency and locking range of the proposed ILFD can be increased without extra chip area and power consumption. The input locking range is 25.4% from 75.1 to 97 GHz at 0-dBm input power without any frequency tun-ing mechanism. The dc power consumption is 2.45 mW with a 0.7-V supply voltage.
The second part is about phase shifter design for 60 GHz phased array system. A RF phase shifter and a LO phase shifter are presented and fabricated in 90 nm CMOS. The quadrature phase rotator (QPR) included vector generator and vector selector is proposed and applied in both phase shifter to achieve 360° phase shift with low phase and amplitude error. The proposed RF phase shifter based on STPS (switch type phase shifter) is all passive and fully digital control with 4 bit resolution. It demonstrates the maximum RMS amplitude error of 0.5 dB and phase error of 5°. Another proposed LO phase shifter based on ILPS (injection-locked phase shifter) exhibits the maximum am-plitude error of ±0.3 dB and phase error of 5°. The output power of the proposed LO phase shifter is -10 dBm with 18 mW dc consumption.

並列關鍵字

CMOS ； frequency divider ； oscillator ； phased array ； phase shifter

參考文獻

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