考慮二圖樣微影感知和自我引導組裝模板配置之細部繞線

DSA-Friendly Detailed Routing Considering Double Patterning and DSA Template Assignments

余海娟(Hai-Juan Yu)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201702890

摘要

隨著集成電路製程技術不斷地縮小，密集的通孔分佈對先進製程和微影技術造成了嚴峻的挑戰。如果單獨考慮用多圖樣微影感知技術來解決通孔密集分佈所造成的一些問題,就需要比較多的光罩數量,然而光罩數量的增加會大大的增加製造成本，進而影響產率。自我引導組裝技術在通孔的打印中表現出了很大的優勢。他通過有限的引導模板，將一些通孔集合在一個模板上，打印出分辨率比較高的通孔。因此，結合自我引導組裝與二圖樣微影感知不僅可以顯著減少通孔層需要的光罩數量，並且可以緩解有效引導模板數量少的限制。在本論文中，基於衝突和兼容圖樣模型，我們提出了結合自我引導組裝和二圖樣微引感知的細部繞線演算法，我們首先設計了線路規劃演算法來減少高密度通孔分佈的區域，接著，我們使用衝突和兼容圖模型來表征自我引導組裝和二圖樣微引感知的特性以便於引導出更好的細部繞線。在細部繞線的過程中，如果存在周圍通孔分佈較多的通孔，我們會先決定這個通孔的引導模板來防止更多的通孔聚集。實驗結果顯示，我們提出的細部繞線演算法在可以有效的減少違反最小間隔的通孔數量，並且使用較少的通孔以及較短的總繞線長度。

關鍵字

實體設計 ； 自我引導組裝 ； 二圖樣微影感知 ； 細部繞線 ； 衝突和兼容圖

並列摘要

As integrated circuit (IC) technology nodes continue to shrink, dense via distribution becomes a severe challenge in both manufacturability and lithography, requiring multiple masks to avoid spacing violations in a via layer. Meanwhile, directed self-assembly (DSA) technique shows great advantages in via printing by employing feasible guiding templates. Combining DSA with double patterning lithography (DPL) can significantly reduce the number of masks for via layers, as well as guiding templates, which is always limited in quantity. In this thesis, we propose a detailed routing algorithm which considers DSA with DPL based on a conflict and compatibility graph model. A net planning algorithm is developed to reduce via-dense areas and decide a prerouting nets order, while the graph model is employed to capture the feature of DSA and DPL to better guide detailed routing. Besides, DSA grouping would be performed in critical vias during detailed routing to avoid attracting more vias inserted in surrounding grids, so as to reduce via-spacing violations. Experimental results demonstrate that our proposed routing algorithm can effectively minimize the number of via spacing violations, with an even smaller total via number

並列關鍵字

directed self-assembly ； double patterning lithography ； detailed routing ； conflict and compatibility graph

參考文獻

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