25-Gb/s 光通訊接收器設計

25-Gb/s Optical Communication Receiver Design

付陽陽(Yang-Yang Fu)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800046

摘要

隨著通訊系統對資料傳送速率的要求越來越高，100-Gb/s 乙太網路系統將開始全面普及。作為乙太網路系統的重要組成部分，光通訊接收器電路的設計顯得尤為關鍵。本論文第一部分介紹了100-Gb/s 乙太網路系統，以及提出了一個突發模式接收器前端電路，可以在幾百納秒以內完成漂移校正。
本論文第二部分提出了一個使用40 納米互補式金屬氧化半導體制程製作之應用於100-Gb/s 乙太網路的25∼28-Gb/s 光通訊接收器，此接收器包括一個RGC 跨阻放大器，若干限幅放大器，連續時間線性等化器，時鐘資料恢復電路以及前饋等化器。此接收器還有一個10-Gb/s 的工作模式，此模式下關閉時鐘資料恢復電路和前饋等化器。RGC 跨阻放大器因為有著更小的輸入電阻，所以在輸入寄生電容一樣的情況下有著更好的頻寬。兩級連續時間線性等化器也可以提供9 dB 的均衡。為了抵消輸出的綁線電感和背板走線的頻寬損失，採用前饋等化器作輸出。
在電域測試中，10-Gb/s 資料在關閉時鐘資料恢復電路模式下靈敏度為1.9mVpp，25-Gb/s 速率下靈敏度為17.6 mVpp，並且誤碼率均小於〖10〗^(-12)，接收器的輸入參考雜訊為2.73 uArms。前饋等化器輸出擺幅為375∼931 mVppd，最大均衡能力為8.5 dB。時鐘資料恢復電路在25-Gb/s 速率下的帶外抖動容忍為0.134 UI，在28-Gb/s 速率下抖動容忍為0.148 UI，鎖定時間在微秒等級。

關鍵字

跨阻放大器，限幅放大器，連續時間線性等化器，時脈資料恢復，前 饋均衡，抖動容忍，靈敏度

並列摘要

The data transmission speed is getting faster and faster in communication system nowadays, 100-Gb/s Ethernet system will be popular. As an important part of the Ethernet system, the design of the optical communication receiver integrated circuits is particularly critical. The first part of this thesis provides a brief description of 100-Gb/s Ethernet system and proposes a burst mode front-end circuit, which can finish DC-offset calibration in hundreds of nanoseconds.
The second part of this thesis presents a 25∼28-Gb/s optical communication receiver for 100-Gb/s Ethernet fabricated in 40nm CMOS. This receiver includes a RGC TIA, several limiting amplifiers (LAs) and two continuous time linear equalizers (CTLEs), a clock and data recovery circuit (CDR), and a feedforward equalizer (FFE). The receiver also has a 10-Gb/s operation mode, we will bypass CDR and FFE in this mode. RGC
TIA has a smaller input resistance, so it has better bandwidth with the same input parasitic capacitance compared with other kinds of TIA. Two-stage CTLEs can provide 0∼9 dB boosting. 3-tap FFE is applied to overcome the channel loss caused by bonding wire and PCB trace.
Testing under electric domain, the sensitivity is 1.9 mVpp for 10-Gb/s mode, and 17.6 mVpp for 25-Gb/s mode, where the bit error rate is less than 〖10〗^(-12), respectively. FFE output swing varies from 375∼931 mVppd, maximum boosting is 8.5 dB. The out-band jitter tolerance is 0.134 UI for 25-Gb/s and 0.148 UI for 28-Gb/s. CDR locking time is in microseconds.

並列關鍵字

transimpedance amplifier ； limiting amplifier ； continuous time linear equalizer ； feedforward equalizer ； jitter tolerance ； sensitivity

參考文獻

[1] J. D’ambrosia, “40 gigabit Ethernet and 100 gigabit Ethernet: The development of a flexible architecture [Commentary],” IEEE Communications Magazine, vol. 47, no. 3, 2009.

[2] B. Razavi, Design of integrated circuits for optical communications. John Wiley & Sons, 2012.

[3] P.-C. Chiang, J.-Y. Jiang, H.-W. Hung, C.-Y. Wu, G.-S. Chen, and J. Lee, “4× 25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 573–585, 2015.

[5] J. Lee and K.-C. Wu, “A 20-Gb/s full-rate linear clock and data recovery circuit with automatic frequency acquisition,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3590–3602, 2009.

[7] M. Rakowski, M. Ingels, K. De Meyer, M. Steyaert, P. Absil, and J. Van Campenhout, “Highly sensitive, low-power, 10-20Gb/s transimpedance amplifier based on cascaded CMOS inverter gain stages,” in Optical Interconnects Conference, 2014 IEEE. IEEE, 2014, pp. 115–116.