高速晶片內收發器之設計與分析

Design and Analysis of High-Speed On-Chip Transceiver

蔡適名(Shih-Ming Tsai)

指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.10108

摘要

在本論文中，設計一個操作在高速串列收發器。在高速收發器的主要問題為晶片中導線的頻寬和晶片中頻率的限制。我們結合4-PAM和多工器/解多工器來解決以上得的問題，並且使用一個平行的偽隨機二進制序列來做晶片自我測試。並達到10Gb/s的傳輸率。

關鍵字

串列 ； 收發器 ； 四電平脈衝調幅 ； 多工器 ； 解多工器 ； 偽隨機二進制序列

並列摘要

In this thesis, the design of a high speed serial link transceiver is presented. The major factors limiting the performance of high-speed transceivers are the bandwidth of the channel. We use a combination of a 4-level pulse amplitude modulation (4-PAM) to reduce the symbol rate to half that of the conventional 2-PAM and high frequency clocks are avoided by multiplexing and de-multiplexing the data directly at the pads. The parallel pseudo-random bit sequence (PRBS) generator for chip self test are examined. The design achieves a 10Gb/s data rate.

並列關鍵字

Serial link ； Transceiver ； 4-PAM ； Multiplexing ； De-multiplexing ； PRBS

參考文獻

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