運用雙向傳輸通道之容錯網路晶片設計

本文提出了一個運用雙向傳輸通道之容錯網路晶片設計，使得網路晶片可以避免靜態或是動態的錯誤傳輸通道，而繼續正常的傳輸溝通。在傳統的網路晶片平台，錯誤的傳輸通道會造成傳輸資料的堵塞或是繞道，進而造成效能上嚴重的影響。這篇論文提出了一個運用可動態調整之雙向傳輸通道的容錯機制，根據所實現的錯誤偵測和診斷機制，使得網路晶片可以精確的避開錯誤通道，且僅伴隨著輕微的效能影響。潛在的效能優勢像是故障率的降低和可靠度的增加也都在本文中仔細的分析。實驗結果說明了在錯誤發生的網路狀態下，對此容錯機制的效能影響不論是在合成交通型態或真實交通型態都是輕微的。除了避免錯誤之外，這篇論文也提出了一個以封包大小為單位的蟲洞交換重傳機制，在網路晶片的資料鏈結層來處理網路晶片發生錯誤的當下而受損害的傳輸資料。實驗結果也分析了在不同的錯誤狀況底下，錯誤對重傳機制的效能變化。

關鍵字

網路晶片；錯誤容忍；重傳；可靠度；雙向傳輸通道

並列摘要

A Bidirectional Fault-Tolerant NoC (BFT-NoC) design capable of mitigating both static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data channel will force blocked packets to make costly detours, resulting in significant performance hits. In this Thesis, novel fault-tolerance measures for a bidirectional NoC platform are proposed. A fault detection and diagnosis mechanism is implemented to determine the fault condition. According to the detected fault condition, the BFT-NoC scheme with reconfigurable bidirectional channels offers great flexibility to sustain data-link faults while incurring negligible performance loss. Potential performance advantages in terms of failure rate reduction and Reliability enhancement of the BFT-NoC architecture are carefully analyzed. Extensive experimental results clearly validate the fault-tolerance performance of BFT-NoC at both synthetic and real world network traffic patterns. In addition to fault avoidance, a packet-basis retransmission mechanism with wormhole switching is investigated to deal with the damaged data caused by the faults. The retransmission performance variation in different fault conditions is also analyzed with the experimental results.

並列關鍵字

NoC ； Fault-Tolerance ； Retransmission ； Reliability ； Bidirectional Channel

參考文獻

[1] W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proc. of the 38th Design Automation Conference, pp. 684-689, Jun. 2001.

[2] L. Benini and G. DeMicheli, "Networks on Chips: a New SoC paradigm," IEEE Computer, Vol. 35, No 1, pp. 70-78, Jan. 2002.

[4] W. Dally and C. Seitz. "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Transactions on Computers, Vol. 36, No. 5, pp. 547–553, May 1987.

[5] L. Benini and G. DeMicheli, Networks on Chips: Technology and Tools, Morgan Kauffmann, 2006.

[8] T. Schonwald, J. Zimmermann, O. Bringmann, and W. Rosenstiel, "Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures," in Proc. of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 527-534, Aug. 2007.

國際替代計量

運用雙向傳輸通道之容錯網路晶片設計

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