系統層級智慧型個人裝置記憶體與儲存子系統效能功耗最佳化

隨著行動運算能力的快速提升，各式各樣的應用程式在個人裝置上變得可能。個人裝置的演進對於記憶體與儲存裝置子系統帶來了新的挑戰。當多個應用程式同時執行時，應用程式之間的記憶體競爭延遲了應用程式記憶體存取的時間史記憶體牆(Memory wall) 的問題更加惡化。記憶體存取時間的延遲使得運算處理單元因為等待記憶體而帶來了不必要的靜態功率(leakage power) 的浪費。為了達到行動裝置的高可靠度，應用程式產生大量的儲存裝置同步寫入(Synchronous write)使系統中的緩衝快取的效益大打折扣進而降低個人裝置的使用者經驗。在這論文之中，我們專注於記憶體與儲存裝置子系統的最佳化。對於記憶體系統，我們提出了一個階層式記憶體排程器(Hierarchical memory scheduler)，用來減少來自不同應用程式的記憶體存取的衝擊並達到公平性的保證。為了減少運算處理單元因為長時間等待記憶體回應造成的靜態功率的浪費，我們提出了一個記憶體存取感知電源門控機制(memory access aware power gating) 得以達到更精確的電源門控判定與控制。對於儲存裝置系統，我們提出了一個階層式DRAM 與PCM 緩衝快取(Hierarchical DRAM and PCM buffer cache) 用來減少儲存裝置同步寫入的衝擊。基於此階層式緩衝快取架構，我們提出了多個緩衝快取管理機制進而提升個人裝置的使用者經驗。

關鍵字

智慧型手機；記憶體排程器；電源門控；緩衝快取

並列摘要

As the mobile computing speed rapidly grows, a variety of applications in the personal devices have been made possible. The evolution of personal devices presents new challenges on the memory and storage subsystems. When multiple applications run together, the memory contention among applications prolongs memory access time, which can exacerbate the long-existing memory wall problem. The long memory access latency also results in unnecessary leakage waste of the processing unit due to the memory stall. To provide high reliability for the mobile devices, applications generate bulk storage synchronous writes, which reduces the benefits of the DRAM buffer cache and degrades the user experience of the personal devices. In this thesis, we focus on the optimization for both memory and storage subsystems in smart personal devices. For the memory system, we propose a hierarchical memory scheduler to reduce the impacts of concurrent memory accesses from different applications with fairness guarantee. To reduce the leakage waste of the processing units due to the long memory latency, we propose a memory access aware power gating mechanism which makes the power gating decisions to those units judiciously. For the storage system, we adopt a hierarchical DRAM and PCM buffer cache to reduce the impacts of synchronous storage writes. Based on the hierarchical buffer cache architecture, we propose the buffer cache management policies to improve the user experience of the personal devices.

並列關鍵字

Smartphone ； Memory Scheduler ； Power Gating ； Buffer Cache

參考文獻

[4] K.-B. Lee, T.-C. Lin, and C.-W Jen. An efficient quality-aware memory controller for multimedia platform SoC. IEEE Trans. Circuits Syst. Video Technol., 15:620–633, May 2005.

[5] A. Burchard, E. H. Nowacka, and A. Chauhan. A real-time streaming memory controller. In Proc. DATE, pages 20–25, 2005.

[6] S.-I. Park, Y. Yi, and I.-C. Park. High performance memory mode control for HDTV decoders. IEEE Trans. Consum. Electron., 49:1348–1353, Nov. 2003.

[8] O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In Proc. MICRO, pages 146–160, 2007.

[9] N. Rafique, W.-T. Lim, and M. Thottethodi. Effective management of dram bandwidth in multicore processors. In Proc. PACT, pages 245–258, 2007.

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系統層級智慧型個人裝置記憶體與儲存子系統效能功耗最佳化

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