一個具有數位延遲轉換器延遲範圍縮小技術且以環形振盪器為基礎之小數型次取樣鎖相迴路

A Ring-VCO-Based Fractional-N Sub-Sampling PLL with a DTC-Range-Reduction Technique

顏浩(Hao Yan)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202202241

摘要

本論文呈獻一個輸入參考時脈信號頻率為60百萬赫茲，操作於24億赫茲，具有數位延遲轉換器延遲範圍縮小技術且以環形振盪器為基礎之小數型次取樣鎖相迴路。此架構運用環形振盪器多相位輸出對量化雜訊的粗略補償，即數位延遲轉換器延遲範圍縮小技術，從而能夠使用高精度及高線性度之數位延遲轉換器，壓制頻寬内的量化雜訊。受益於次取樣鎖相迴路和數位延遲轉換器延遲範圍縮小技術，故此架構可利用6百萬赫茲高頻寬壓制環形振盪器雜訊，以達成低的頻寬外雜訊。本論文采用多個數位校正迴路包括數位延遲轉換器增益誤差校正迴路，次取樣電荷泵和比較器輸入偏移誤差抵消迴路和環形振盪器相位誤差補償迴路，以降低實際電路非線性的影響，以至於此頻率合成器能達到極佳的表現。

這個架構在九十奈米製程所設計。其主要面積為0.07537平方毫米且在1 伏特的電源供應下總共消耗10.18毫瓦。在24億赫茲操作下，相對於主頻率1百萬赫茲處模擬到的相位雜訊為 -116.7 dBc/Hz。其均方根抖動量為479.6飛秒 (積分範圍為10千赫茲到40百萬赫茲)，品質因數(figure-of-merit)為 -236.3 dB。參考突波為 -64.4 dBc且小數突波小於 -60 dBc。

關鍵字

小數型次取樣鎖相迴路 ； 環形振盪器多相位輸出 ； 數位延遲轉換器延遲範圍縮小技術 ； 數位校正迴路

並列摘要

This thesis presents a 2.4-GHz ring-VCO-based fractional-N sub-sampling phase-locked loop with a 60-MHz input reference clock and a digital-to-time converter delay range reduction technique. This architecture uses the ring-VCO multi-phase outputs to coarsely compensate the quantization noise (that is the digital-to-time converter delay range reduction technology) so that the digital-to-time converter with high precision and high linearity can be designed to suppress the quantization noise in the loop bandwidth. Benefiting from sub-sampling phase-locked loop and digital-to-time converter delay range reduction technology, the architecture can suppress ring-VCO phase noise with a high loop bandwidth of 6 MHz to achieve low out-of-loop-bandwidth noise. Multiple digital calibration loops including DTC gain error calibration loop (DTCGL), VCO phase mismatch compensation loop (PMCL), SSCP and comparator offset mismatch cancellation loop (OFMCL) are proposed to reduce the effects of real circuits nonlinearity, so that this frequency synthesizer can achieve excellent performance.

This architecture is implemented in a 90nm CMOS process. The core area is 0.07537 mm2 and consumes a total of 10.18 mW with the 1-V power supply. At 2.4 GHz, the simulated phase noise at 1 MHz offset is -116.7 dBc/Hz. Its rms jitter is 479.6 fs (integrated from 10 kHz to 40 MHz) and figure-of-merit is -236.3 dB. The reference spur is -64.4 dBc and the low fractional spur is less than -60 dBc.

並列關鍵字

Fractional-N sub-sampling phase-locked loop ； ring-VCO multi-phase outputs ； digital-to-time converter delay range reduction technique ； digital calibration loops

參考文獻

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