以系統層次觀點驗證串流進階配接器模型

System Level Verification for Serial Advanced Technology Attachment Models

沈哲永(Che-Yang Shen)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00536

摘要

隨著科技日新月異, 以及系統晶片(System-on-a-Chip) 的推廣, 現今的晶片設計複雜度, 由於規格多以系統的層次去規範; 因此, 在此層級下的晶片設計, 將比以往的設計更具挑戰性, 且更難以作完整性的功能性涵蓋率(Functional Coverage)驗證。 為了加速系統晶片的設計流程, 許多廠商紛紛推出新系統設計語言, 如: SystemC、SystemVerilog ...等。 雖然已包涵許多新的驗證工具在其中, 但效率仍然是相當地有限。

為了彌補系統設計以及系統驗證這兩者之間的差距, 本論文提出如何有效率地提升功能性涵蓋率的方法, 並以現今最熱門的儲存元件傳輸介面---Serial ATA Interface 為主題, 來實作並驗證 SATA/SATAII 模型。 此模型也就是所謂的功能性匯流排模型(Bus Functional Model)。 其採用 Verilog 行為語法與功能強大的驗證套件---TestWizard 所提供的 VLE 環境; 因此, 我們能夠
在系統晶片完成之前, 即能將功能性匯流排模型快速地實作出來。

此外, 也提供以 Transaction-based 為基準, 以 Assertion-based 為輔助的驗證環境。 藉由這兩種方式的結合, 以往晶片驗證的時間能被有效地縮短, 且以系統層次為概念的驗證方法得以實現, 更使得晶片驗證工程師(Verification Engineer)與晶片設計工程師(Hardware Engineer)的工作能夠即時地分工進行。

由於本論文提出的驗證環境以及功能性匯流排模型, 均是以現今業界最熱門的硬體描述語言---Verilog 為主要的設計語言;因此, 這將使得晶片整合(Chip Integration)更加容易、快速且達成 Time-to-Market 的最終目的。

關鍵字

驗證 ； 系統驗證 ； 串流進階配接器 ； 配接器 ； 串流配接器

並列摘要

With the growth of CPU rate, the system performance depends on the speed of the system bus or the peripherals connected to it. Obviously, Parallel ATA is such a case and causes the loss of system performance. Thus, in order not to let such a situation exist, the best solution to storage interface is to replace the legacy Parallel ATA by the Serial ATA interface. Unfortunately, the traditional way to verify a design is time consuming since it's not applied from system point of view. As a result, system level verification and implementation become the main stream methodology and more and more significant nowadays.

In this thesis, I'll introduce a quick implementation methodology (using bus functional model, or so-called transaction verification model) to construct a set of system models for SATA and SATAII. Those models are
spec-oriented and can be viewed as virtual circuits since their behavior is just the same as the real circuits'. A SATA or SATAII interface is composed of four layers, which are physical layer, link layer, transport layer, and application layer respectively. With layered approach, throughput of SATA/SATAII interface can be further facilitated.

As mentioned above, verification from system point of view plays an important role when design is getting large. Hence, I'll provide several system verification techniques, such as transaction-based verification, assertion-based verification, coverage-based verification and so on, applied to either our BFMs or user's DUTs (device under test) for better functional coverage.

並列關鍵字

Verification ； System Level Verification ； Serial ATA ； SATA ； Serial Advanced Technology Attachment Models

參考文獻

6),” September 2002.

January 2006.

[13] Ting-Chun Huang, “A Functional Verification Environment for Advanced

Switching Architecture,” Master Thesis, Graduate Institute of

Electronics Engineering, National Taiwan University, 2004.