利用MTCMOS技術實現低功率SOC系統晶片佈局最佳化

Layout Optimization Using MTCMOS Technique for Low-Power SOC Applications

黃金煌(Chin-Huang Huang)

指導教授 ： 郭正邦

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.10348

摘要

這篇論文主要是在利用MTCMOS技術透過EDA工具來對晶片Layout來做優化。第一章首先介紹近年來互補式金氧半的發展演進，第二章開始介紹MTCMOS技術與其應用，接下來是電子設計自動化技術在晶片積體電路設計中的應用，包含電路中的功率消耗分析和時序分析。第三章則是介紹使用MTCMOS的優化方法來對晶片做功率消耗分析，針對我們使用的兩種不同的MTCMOS演算法來做比較，最後在對優化過後的晶片做重新擺放來解決熱點叢聚的問題。第四章為結論和未來研究方向。

關鍵字

佈局最佳化

並列摘要

This thesis presents the method of using the MTCMOS technology to optimize the SOC chip considering layout via EDA tools. Chapter 1 presents the recent CMOS VLSI SOC design circuit trend. Then Chapter 2 describes MTCMOS technology and its applications. The application of electronic design automation in SOC circuits is presented, including the power consumption analysis and timing analysis. Chapter 3 presents the method of power consumption analysis of the low power SOC chip using MTCMOS technology. Two MTCMOS algorithms are presented for compared. At last a procedure of placement is performed on an SOC chip to solve the problem of clustering hotspots. Chapter 4 is the conclusion and future work.

並列關鍵字

MTCMOS

參考文獻

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