運用數位演算法的10Gb/s可適應等化器

A 10Gb/s Equalizer with a Digital Adaptive Algorithm

蕭瑞成(Jui-Cheng Hsiao)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10448

摘要

本論文提出一個使用數位自適應性演算法來取代電阻電容濾波器、整流器; 電壓電流轉換器和大容值迴路電容的等化器。所提出的演算法利用了兩個類比性的參考電位來分別表示輸入資料的高頻成份與低頻成份。藉由監測這兩個參考電位，所提出的等化器可以適當地調整自身的高頻增益去補償通道的損耗。當輸入資料為8十億位元毎秒時，經過一個90公分的通道以後所量測得到的峰對峰抖動值從81.63皮秒下降到33.84皮秒。而當輸入資料為10十億位元每秒時，經過一個37公分的通道以後所量測得到的峰對峰抖動值從47.64皮秒下降為37.60皮秒。由此可證，所提出的自適應性等化器能夠成功地對不同長度(可達90公分)的FR-4印刷電路板進行有效的補償。這項成果已經透過40奈米的製程實現，其核心電路面積為0.014平方毫米。在1伏特的電源供應下扣除輸出緩衝器的功耗後，此等化器共消耗10毫安培。所提出的等化器只使用了數位邏輯閘來進行自適應性調整而非電阻電容濾波器、整流器、電壓電流轉換器及用來讓迴路穩定的大容值電容。此種數位集中式的實現方法在先進的互補式金屬氧化物半導體製程下能夠大幅度地減少硬體的成本。

關鍵字

自適應性等化器 ； 數位自適應性演算法

並列摘要

An equalizer using a digital adaptive algorithm is proposed to replace RC filters, rectifiers, V/I converters and large loop capacitors. The proposed algorithm uses two analog reference levels to represent the high-frequency and low-frequency components of the input data, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. The measured peak-to-peak jitter for the 90-cm channel is reduced from 81.63 ps to 33.84 ps with 8-Gb/s input data; while the 37-cm channel is decreased from 47.64 ps to 37.60 ps with 10-Gb/s input data. The proposed adaptive equalizer successfully operates for different channel lengths (up to 90-cm) on FR-4 PCB. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply (excluding output buffer circuits). The proposed equalizer uses only digital logic gates for adaptation instead of RC filters, rectifiers, V/I converters and large capacitors for loop stabilization. Such digital-intensive implementation can highly reduce the hardware cost in advanced CMOS technologies.

並列關鍵字

Adaptive equalizer ； digital adaptive algorithm

參考文獻

[1] Gondi, S. and Razavi, B., “Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp.1999-2011, Sept. 2007.

[2] Uchiki, H., Ota, Y., Tani, M., Hayakawa, Y. and Asahina, K., “A 6-Gb/s RX equalizer adapted using direct measurement of the equalizer output amplitude,” IEEE ISSCC Dig. Tech. Papers, pp. 104-105, Feb. 2008.

[3] Y.-M. Ying and S.-I. Liu, “A 20Gb/s digitally adaptive equalizer/DFE with blind sampling,” IEEE ISSCC Dig. Tech. Papers, pp. 444–446, Feb. 2011.

[4] Jri Lee, "A 20-Gb/s adaptive equalizer in 0.13-um CMOS technology," IEEE J. Solid-State Circuits, vol.41, no.9, pp.2058-2066, Sept. 2006.

[5] H. Y. Joo and L. S. Kim, "A data-pattern-tolerant adaptive equalizer using the spectrum balancing method," IEEE Trans. Circuits and Systems II, vol.57, no.3, pp.228-232, Mar. 2010.