浮動閘極材料系統在電晶體式記憶體的應用

Floating-gate Material Systems for Transistor-type Memory Devices

張亘鈞(Hsuan-Chun Chang)

指導教授 ： 陳文章

國立臺灣大學/工學院/化學工程學研究所/博士(2015年)

https://doi.org/10.6342/NTU.2015.01046

摘要

中文摘要
　　近年來有機記憶元件由於具有可撓曲、尺寸與材料結構多樣化等優勢，受到廣泛關注。一個典型的有機電晶體式記憶體元件是浮動閘極記憶體。在這種元件當中，載子被儲存在金屬抑或是半導體則被稱作浮動閘極，位於絕緣介電層內，並且完全由絕緣體包圍。然而，浮動閘極結構對記憶體的影響尚未有系統性的研究。在此論文中,我們呈報自組裝單分子層的修飾在記憶體特性上的影響。我們進一步研究具有施體/受體介面的有機異質電晶體其對於電性上的展現。此外，針狀C60/酞菁銅(CuPc)奈米粒子的雙浮動閘極在低電壓下操作的非揮發性記憶體元件也進行了研究。下面總結一下本文的重要發現。
　　本文的第一部分(第二章)- 藉由自組裝單分子層改善有機浮動閘極式記憶體特性-自組裝單分子層介面的修飾顯著改善遲滯，記憶體視窗和零偏壓下的電流開關比。這浮動閘極式記憶體在短時間內（小於一秒）操作電壓爲100 V，在寫入/抹除的過程顯示出一個大的記憶體視窗可以達到190 V和105電流開關比。此外，該元件對於雙穩定掃描顯示出極好的非揮發特性，對於五氟苯基丙基三甲氧基矽烷（FB-SAM）修飾的元件可以穩定且維持開與關的狀態103秒及106電流開關比。
　　本文的第二部分(第三章)- 非揮發性有機薄膜電晶體式記憶體基於高分子半導體混摻金奈米粒子的混合複合材料：我們呈報一個有利於製造且利用混合奈米複合材料的非揮發性有機薄膜電晶體式記憶體，使用半導體9,9-二辛基-alt-噻吩（F8T2）和具有配位基的金奈米粒子從而提供一個電荷儲存層的媒介。電壓掃描的施予有效地調節載子遷移透過9,9-二辛基-alt-噻吩通道以及載子捕捉在官能化的金奈米粒子裡。混合式記憶體能有效地控制加入的金奈米粒子濃度（0至9 %）以及不同碳鏈長度配位基的金奈米粒子(Au-L6, Au-L10, and Au-L18)。藉由電壓掃描，高濃度和較短碳鏈配位基的金奈米粒子大大增加了記憶體視窗。混合奈米複合材料9,9-二辛基-alt-噻吩: Au-L6提供了有機薄膜電晶體式記憶體~41 V記憶體視窗在操作電壓±30 V和至少103 秒的數據保留。
本文的第三部分(第四章)- 一維靜電紡絲P3HT:金奈米粒子之混成奈米纖維應用於可撓取式非揮發性記憶體-一個使用一維（1D）靜電紡奈米纖維的聚（3 - 己基噻吩）（P3HT）：金納米粒子混合通道製備新穎的非揮發性快閃電晶體式記憶體在聚乙烯酯（PEN）軟性基板上。金納米粒子以自組裝單分子薄膜（SAM）之對苯硫酚基的對位取代氨基（Au-NH2），甲基（Au-CH3）或三氟甲基（Au-CF3）尾基官能化。以低操作電壓±5伏特，混合奈米纖維電晶體式記憶體呈現出3.5∼10.6 伏特門檻電壓位移和至少104 秒的數據保留，以及約100次的寫入/抹除應力耐力下具有最小的影響。即使是彎曲的條件下（半徑5∼30毫米）或1000反覆彎曲循環，元件依然保持可靠性和穩定性。　　
本文的第四部分(第五章)- 使用施體/受體平面異質結構有機場效電晶體的一維電紡奈米纖維通道-根據電紡P3HT奈米纖維/熱蒸鍍F16CuPc有機平面p-n異質結構作為主動層之電晶體，透過調控F16CuPc厚度之單極性p型非揮發性記憶體以及雙極性元件已經被研究。
　　本文的第五部分(第六章)- 單晶C60針/奈米粒子酞菁銅(CuPc)之低電壓操作雙浮動閘極有機電機晶體式非揮發性記憶體元件-雙浮動閘極元件結構是經由單晶C60針(N-C60)/奈米粒子酞菁銅(CuPc)覆蓋交聯poly(4-vinylphenol) (c-PVP)當作穿遂障礙的異質結構雙電荷層所形成。對於先前的研究而言，分散的p型CuPc奈米顆粒以及n型N-C60被獨立地選擇當作電洞以及電子的捕捉位置，增進了記憶體視窗和資料儲存的能力，N-C60捕捉位置(直徑∼590±15 奈米) 上方直接熱蒸鍍CuPc納米顆粒在氧化鉿基材上。在雙浮動閘極元件的記憶體特性進行了系統性的研究相較於單浮動閘極的記憶體結構。
我們的研究顯示出自組裝單分子層，施體/受體的異質結構以及雙浮動閘極對製備成一先進的電荷儲存元件的重要性。

關鍵字

電晶體式記憶體 ； 奈米浮動閘極 ； 雙浮動閘極 ； 電紡奈米纖維 ； 雙極性捕捉 ； 自組裝單分子層

並列摘要

Abstract
Organic-based memory devices have received extensive scientific interest due to their advantages of flexibility, scalability, and material variety. A typical type of charge-trapping OFET memory is organic floating-gate memory. In this device, charges are stored in a metal or in a semiconducting layer called a floating gate, located within the insulating gate dielectric, and completely surrounded by insulator. However, there is no systematic study on the above structure effects. In this thesis, we report the effects of self-assembled monolayer (SAM) modification on the electrical memory characteristics. We further explored the organic heterojunction transistor with donor/acceptor interface on the electrical characteristics of transistor-type memory devices. Additionally, the C60 Needle/CuPc Nanoparticle Double Floating-Gate for the low-voltage nonvolatile memory devices were also investigated. The following summarize the important discovery of this thesis.
1. Improving the characteristics of an organic nano floating gate memory by a self-assembled monolayer (Chapter 2): SAM-based interfacial engineering significantly improved the hysteresis, memory window, and on/off ratio of a nano floating gate memory (NFGM) at zero gate voltage. This NFGM showed a large memory window of up to 190 V and on/off current ratio of 105 during writing and erasing with an operation voltage of 100 V of gate bias in a short time, less than 1 s. Furthermore, the devices show excellent nonvolatile behavior for bistable switching. The ON and OFF state can be stably maintained for 103 s with an Ion/Ioff current ratio of 106 for a pentafluorophenyl trimethoxysilane (FB-SAM) modified device.
2. Nonvolatile Organic Thin Film Transistor Memory Devices Based on Hybrid Nanocomposites of Semiconducting Polymers: Gold Nanoparticles (Chapter 3): Organic thin film transistor (OTFT)-based nonvolatile memory devices using the hybrid nanocomposites of semiconducting poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and ligand-capped Au nanoparticles (NPs), thereby serving as a charge storage medium. Electrical bias sweep/excitation effectively modulates the current response of hybrid memory devices through the charge transfer between F8T2 channel and functionalized Au NPs trapping sites. The electrical performance of the hybrid memory devices can be effectively controlled
though the loading concentrations (0−9 %) of Au NPs and
organic thiolate ligands on Au NP surfaces with different carbon chain lengths (Au-L6, Au-L10, and Au-L18). The memory window induced by voltage sweep is considerably increased by the high content of Au NPs or short carbon chain on the ligand. The hybrid nanocomposite of F8T2 : 9% Au-L6 provides the OTFT memories with a memory window of ∼41 V operated at ±30 V and memory ratio of ∼1 × 103 maintained for 1 × 104 s.
3. Flexible Nonvolatile Transistor Memory Devices Based on One-dimensional Electrospun P3HT:Au Hybrid Nanofibers (Chapter 4): A novel flexible nonvolatile flash transistor memory devices on flexible polyethylene naphthalate (PEN) substrate using one-dimensional (1D) electrospun nanofiber of poly(3-hexylthiophene) (P3HT):gold nanoparticles (Au NPs) hybrid as the channel. The Au NPs are functionalized with self-assembled monolayer (SAM) of para-substituted amino (Au-NH2), methyl (Au-CH3) or trifluoromethyl (Au-CF3) tail groups on the benzenethiol moiety. With the low operation voltage of ±5 V, the hybrid nanofiber transistor memories exhibit a 3.5~10.6 V threshold voltage shifting and at least 104 s data retention, with a minimum effect on ~100 programmed/erased stress endurances. The devices remain reliable and stable even under the bending conditions (radius: 5~30 mm) or 1000 repetitive bending cycles.
4. One-Dimensional Electrospun Nanofiber Channel for Organic Field Effect Transistor using Donor/Acceptor Planar Heterojunction Architecture (Chapter 5): Organic planar p-n heterojunction transistors based on electronspun poly(3-hexlthiophene) (P3HT) nanofibers/thermally deposited copper hexadecafluorophthalocyanine (F16CuPc) active layer have been developed for unipolar p-type nonvolatile memory and ambipolar device through simple tuning of top F16CuPc capping layer thickness.
5. Single-Crystal C60 Needle/CuPc Nanoparticle Double Floating-Gate for Low-Voltage Organic Transistor Based Non-volatile Memory Devices (Chapter 6): The double floating-gate device structure was formed from the semiconducting channel and heterostructured dual chargeable layers of CuPc NPs/single crystal C60 needles (N-C60) covered by crosslinking poly(4-vinylphenol) (c-PVP) tunneling barrier. Discrete p-type CuPc NPs and n-type N-C60 were independently selected as the hole and electron trapping sites for the above double floating-gate transistor memory to further enhance memory window and related data storage capacity. N-C60 trapping sites (diameters~590±15 nm) were first fabricated and then thermal-evaporated CuPc NPs (~15±3 nm) were deposited discretely on the N-C60 or the HfO2 interface. A systematic investigation on memory characteristics of double floating-gate devices were impartially compared to those of individual single floating-gate memory structure (N-C60 or CuPc-only devices)
Our study revealed the significance of the self-assembled monolayer, donor/acceptor heterojunction architecture and double floating gate on the OFET memory characteristics for advanced data storage applications.

並列關鍵字

transistor-type memory ； nano floating gate ； double floating gate ； electrospun nanofiber ； ambipolar trapping ； self-assembled monolayer

參考文獻

2. C. D. Dimitrakopoulos and P. R. L. Malenfant, Adv. Mater., 2002, 14, 99.

3. W. L. Leong, N. Mathews, B. Tan, S. Vaidyanathan, F. Dotz and S. Mhaisalkar, J. Mater. Chem., 2011, 21, 5203.

4. J. H. Tsai, W.-Y. Lee, W.-C. Chen, C.-Y. Yu, G.-W. Hwang, C. Ting, Chem. Mater., 2010, 22, 3290.

12. Y. Yang, J. Ouyang, L. P. Ma, R. J. H. Tseng, C. W. Chu, Adv. Funct. Mater., 2011, 16, 1001.

13. T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, M. Takamiya, T. Sakurai, T. Someya, Science, 2009, 326, 1516.