隨著網際網路近年來的蓬勃發展,加上網路多媒體服務的崛起,通訊系統的傳輸頻寬需求也變得越來越高。西元2002年八月,國際電子電機工程師協會(Institute of Electrical and Electronics Engineers) 802.3a工作小組制訂了百億位元乙太網路的10G Base LX4系統的標準規格。當傳輸速度達到每秒百億位元符碼的數量級時,光纖已經不再是過往認定的理想傳輸介質。由於傳統的回饋等化器(Decision Feedback Equalizer)受限於謬誤延遲(Error Propagation),因此無法達到10G Base LX4系統中位元錯誤率(Bit Error Rate)為10-12的標準。為了解決此問題,我們決定採用「軟基準多層級決策可適應性回饋等化器」(Soft-Threshold Multi-layer Adaptive Decision Feedback Equalizer)來降低位元錯誤率,藉以提高系統效能。軟基準多層級決策可適應性回饋等化器不但可提高系統效能,達到所要求之位元錯誤率,並且可降低類比/數位轉化器(Analog/Digital Converter)所需之位元精確度兩位元,降低了高速類比/數位轉化器設計的困難度。我們將軟基準多層級決策可適應性回饋等化器與前端類比等化器整合,亦大量化簡了數位等化器所需之硬體成本。本論文亦對軟基準多層級決策可適應性回饋等化器提出了管線化兩級前看式的超大積體電路設計架構來提昇系統之操作頻率。
As the applications and prevalence of the world wide web (WWW) flourish over the past decade, the demand for higher bandwidth and data rate is skyrocketing. In August 2002, the IEEE 802.3ae task force finalized the 10-Gigabit Base LX4 Ethernet Standard. However, under multi-gigabit data rates, fiber is no longer an ideal transmission medium. This is especially the case for multi-mode fiber (MMF) used in 10G Base LX4 Ethernet systems, because it suffers from differential mode dispersion (DMD). However, conventional adaptive decision feedback equalizers (ADFE) cannot attain the bit error rate (BER) requirement of 10-12 in 10G Base LX4 Ethernet systems, because hard decision of slicers causes error propagation in the feedback loop. Soft threshold multi-layer adaptive decision feedback equalizer (STM-ADFE) designs are adopted to solve this problem. Our system simulation environment includes three representative channel impulses responses, trans-impedance amplifier (TIA), analog equalizer (AEQ), analog/digital converter (ADC), and STM-ADFE. Integration with the analog front end reduces the filter tap numbers needed in STM-ADFE. VLSI architectures of STM-ADFE are also presented. With low hardware overhead, STM-ADFE not only lowers the BER, but also reduces the bit resolution needed in the ADC from 8 to 6.