40 奈米部份解離絕緣體上矽金氧半元件浮動基體效應之雙載子電晶體模型

Modeling the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect

陳嘉興(Chia-Hsing Chen)

指導教授 ： 郭正邦

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01231

摘要

在本論文中，描述使用40 奈米部份解離絕緣體上矽金氧半元件在不同頻率下之導通與關閉的暫態分析
第一章中介紹絕緣體上矽金氧半(SOI)元件及其元件特性，並對部分解離絕緣體上矽金氧半元件(PDSOI)進行探討。
在第二章將建立一個適用於暫態分析的等效電路模型，在更高的上升時間下，汲極電流會因內部寄生雙載子電晶體之電流增益增大而變，較小的位移電流與實驗數據可以驗證。
在第三章將討論在不同的下降時間下，部分解離絕緣體上矽金氧半元件之其暫態的分析。在更高的下降時間下內部寄生雙載子電晶體之M-1 會相對變小，藉由模擬元件內部載子分佈情形，當操作頻率降低，撞擊游離效應將不明顯。
第四章為論文總結與未來工作

關鍵字

暫態分析 ； 寄生雙載子電晶體 ； 絕緣體上矽金氧半

並列摘要

This thesis reports modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modeled.
During the turn-on transient by imposing a step voltage from 0V to 2V at the gate, the case with a slower rise time shows a faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured results.
During the turn-off transient by imposing a step voltage from 2V to 0V at the gate, the case with a faster fall time shows a faster turn-off in the drain current due to a stronger function of the parasitic bipolar device. With a slower fall time shows a bigger multiplication factor imply stronger impact ionization , Verified by the experimentally measured data and the 2D simulation results, Chapter 4 is conclusion and future work.

並列關鍵字

transient analysis ； Parasitic Bipolar Device ； SOI MOS

參考文獻

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[2]K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics, “ Proc. Of IEEE, 85(4), 558-576, 1997.

[3]S. S. Chen and J. B. Kuo, “An Analytical CAD Kink Effect Model of Partially-Depleted SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, Vol. 41, No. 3, pp. 447-458, March 1997.

[4]J. B. Kuo, “Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2001.

[5] H. J. Hung, J. B. Kuo, D. Chen, C. T. Tsai an C. S. Yeh, ”Shallow Trench Isolation-Related Narrow Channel Effect on the Kink Effect Behavior of 40nm PD SOI NMOS Device, ”Solid State Electronics, Vol. 54, No. 1, Jan. 2010