透過您的圖書館登入
IP:3.145.151.141
  • 學位論文

極化碼在快閃記憶體中更正能力提升之主動式通道調整策略

Proactive Channel Adjustment to Improve Polar Code Capability for Flash Storage Devices

指導教授 : 郭大維
共同指導教授 : 張原豪

摘要


並列摘要


Low-density parity-check (LDPC) codes have made a great success on correcting errors in flash storage devices, but its hardware cost and error correction time keeps increasing as the error rate of flash memory keeps increasing. To improve the lifetime of devices, researchers are seeking alternative methods. Fortunately, with the low encoding/ decoding complexity and the high error correction capability, polar code with the support of list-decoding and cyclic redundancy check can outperform LDPC code in the area of data communication. Thus, it also draws a lot of attentions on how to adopt and enable polar codes in storage applications. However, the code construction and encoding length limitation issues obstruct the adoption of polar codes in flash storage devices. To enable polar codes in flash storage devices, we propose a proactive channel adjustment design to extend the effective time of a code construction to improve the error correction capability of polar codes. This design pro-actively tunes the quality of the desirable flash cells to maintain the correctness of the code construction and relax the constraint of encoding length limitation. A series of experiments was conducted to evaluate the efficacy of the proposed design. It shows that the proposed design can effectively improve the error correction capability of polar codes in flash storage devices.

參考文獻


[1] E. Arikan. Channel polarization: A method for constructing capacity achieving codes for symmetric binary-input memoryless channels. 55(7):3051–3073, Jul 2009.
[2] Raj Chandra Bose and Dwijendra K Ray-Chaudhuri. On a class of error correcting binary group codes. Information and control, 3(1):68–79, 1960.
[3] Yu Cai, Erich F Haratsch, Onur Mutlu, and Ken Mai. Error patterns in mlc nand flash memory: Measurement, characterization, and analysis. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 521–526. EDA Consortium, 2012.
[4] Yu Cai, Erich F Haratsch, Onur Mutlu, and Ken Mai. Threshold voltage distribution in mlc nand flash memory: Characterization, analysis, and modeling. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pages 1285–1290. IEEE, 2013.
[5] Jaewon Cha and Sungho Kang. Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices . ETRI Journal, 35(1):166–169, Feb 2013.

延伸閱讀