- 學位論文
設計與實作一個快速分析多執行緒應用程式效能之多核心系統模擬環境
A Rapid Simulation Environment for Application Performance Estimation on Parameterized Multi-core/Multi-threading Architecture Models
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並列摘要
The technique of increasing clock rate to speed up the application performance have reached bottlenecks such as power dissipation, design complexity, and diminishing returns from increasing Instruction Level Parallelism (ILP) supportcite{LDMoore}. Therefore, computer architects have designed multi-core processors by placing two or more processing cores on the same chip. However, with increasing number of cores, the simulation run time increases due to simulation complexity and its code size. These large simulation time limits the ability to predict the application performance during the design phase. In this study, we propose a performance evaluation framework aim to give a quick estimation of performance during early design phases. The framework achieves speedup by putting architecture-independent characteristics of an application into its application model and simulating the application model with a high level architecture model. We use MiBench, which is a a free, commercially representative embedded benchmark suite as our evaluation test case and verify the results by comparing it with a robust cycle-accurate simulator, ARM SoC designer. For homogenous workloads on the single-core, the dual-core, and the 4-core system, we got an average of 2.1X speedup over the ARM SoC designer. For the error rate, we got the average of 0%, 5%, 11% on the single-core, dual-core, and 4-core system. The workload bitcount has a highest error rate of all benchmarks. We propose several schemes to reduce the errors as the potential future work.
參考文獻
[1] “The Lives and Death of Moore’s Law.” http://www.firstmonday.org/issues/issue7 11/tuomi/.
at Intel Magazine, July 2005.
[3] V. Narasiman and A. Suleman, “A literature survey of effective techniques to reduce
simulation time.”
[4] “MiBench Version 1.0.” http://www.eecs.umich.edu/mibench/.
延伸閱讀
- Lee, H. C. (2011). 虛擬平台中多核心系統之效能模型與評估 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2011.10204
- Hsu, S. J. (2007). 建構於多處理器即時作業系統上的一個適應性排程器 [master's thesis, Tatung University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0081-0607200917241039
- Chang, C. C. (2011). 多執行緒程式在多核處理器之自動化相位偵測與分類工具 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2011.01395
- Wang, S. C. (2010). 異質多核心上之程式設計模型評估與設計 [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-1901201111412454
- Jiang, C. F., Wan, J., Xu, X. H., Zhang, J. L., & You, X. D. (2013). Resource Allocation in Contending Virtualized Environments through Stochastic Virtual Machine Performance Modeling and Feedback. Journal of Information Science and Engineering, 29(2), 299-327. https://doi.org/10.6688/JISE.2013.29.2.7