- 學位論文
24至36-GHz六倍頻器與77-GHz疊接放大器之研製
Research of 24 to 36-GHz Sixtupler and 77-GHz Cascode Amplifiers
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摘要
本論文分為兩個部份。第一部分為倍頻器，第二部分為放大器，皆採用0.15微米低雜訊假晶高速電子遷移率電晶體製程製作。 第一部份為描述24至36-GHz六倍頻器。此電路是由二倍頻器、緩衝放大器以及三倍頻器所組成。在元件選取、級間分析、阻抗匹配以及穩定性分析上亦會詳加說明。此電路於輸入功率為 -7 dBm、輸出頻率為30 GHz時，轉換增益約5.3 dB，且在同樣的輸入功率下，基頻壓制比 -60 dB好，其它倍頻之諧波壓制在輸出頻率24 GHz至31.5 GHz間，皆小於 -10 dB。 第二部分描述77-GHz低雜訊放大器及77-GHz緩衝放大器，兩個電路皆以疊接組態設計，並應用在77-GHz開–關鍵移系統。當電路操作在高頻時，較難掌握電晶體模型內的參數，模擬與量測會產生差異。為了得到更好的一致性，萃取測試電路的小訊號參數及直流參數來建立Angelov模型。除了模型的準確度外，在佈局砷化鎵電晶體疊接組態的電路時，由背板導孔造成的電感效應會影響疊接組態的第二級電路閘極處之旁路電容，甚至使電路振盪。因此利用接地共面波導的電路佈局的方式減低此效應。最後，兩個放大器在77-GHz小訊號增益量測結果分別為22 dB、15 dB，而頻率同為77 GHz下，輸入功率為 -15 dBm時，輸出功率分別為2.7 dB及 -1 dB，消耗的直流功率分別為28.5 mW及29.5 mW。
並列摘要
This thesis consists of two parts. The first part is frequency multipliers and the second part is amplifiers. These circuits are implemented using 0.15-um low-noise pseudomorphic high electron mobility transistor (low-noise pHEMT) technology. The first part introduces a 24-36 GHz sixtupler consisting of a doubler, a buffer and a tripler. The details of device selection, inter-stage analysis, impedance matching and stability analysis will also be discussed. The measured conversion gain is about 5.3 dB at 30-GHz output frequency with input power of -7 dBm. Under the same input power, the measured result of harmonic suppression shows fundamental harmonic suppression is better than -60 dB and the other harmonic suppressions are better than -10 dB between 24 GHz to 31.5 GHz. The second part presents a 77-GHz low-noise amplifier and a 77-GHz buffer amplifier. Both circuits are used cascode configuration and also applied as a 77-GHz on-off keying system (OOK system). Because of the inaccuracy of the transistor model provided by the semiconductor foundry, the simulation result do not agree well with the measurement result at high frequency. To achieve a better agreement, Angelov model is generated by extracting dc parameters and small signal parameters of a test-key device. In the circuit design, device selection and impedance matching are based on the modified model. Beside the accuracy of the transistor model, grounded coplanar waveguide (GCPW) structure are utilized in order to decrease the inductive effect of the cascode configuration in GaAs pHEMT process due to the backside via hole. The measured small signal gain of the low-noise amplifier and the buffer amplifier are 22 dB and 15 dB, respectively. Under input power of -15 dBm, the measured output power result of the low-noise amplifier and the buffer amplifier are 2.7 dB and -1 dBm and the dc consumption are 28.5 mW and 29.5 mW, respectively.
參考文獻
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