應用發光電晶體整合光電邏輯閘與光電SR閂鎖器之研究與開發

Investigation and Development of Light-Emitting Transistors Based Optical Logic Gate and Optical SR Latch

陳宣翰(Hsuan-Han Chen)

指導教授 ： 吳肇欣

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201903506

摘要

發光電晶體(Light emitting transistors, LETs)的自發性復合載子生命週期為皮秒等級，因此具有高速的光調變頻寬，元件結構亦可同時作為光接收器、調變器與光發射器，再加上特有的光電雙輸出特性，使發光電晶體成為下一代光電積體整合電路(Opto-Electronic Integrated Circuits, OEICs)的重點發展元件。
第一部分探討發光電晶體作為異質接面光電晶體(Heterojunction phototransistor, HPT)與光二極體(Photodiode, PD)的特性差異，光電晶體由於具有內部增益，故擁有較大的光響應度，然而複雜的物理機制與結構，同時犧牲其光調變速度。本論文提出全新的雙端光電晶體等效小訊號電路模型，並探討影響光調變速度的關鍵參數，發現微縮光電晶體尺寸與增加入射光強，可有效提升元件的光響應截止頻率。在光二極體的高頻特性上，微縮元件同樣可提升其光調變速度。
第二部分設計以發光電晶體和光偵測器所組成的光電邏輯閘，其具有同時傳輸電訊號NAND閘與光訊號AND閘的光電雙輸出特性，並成功展示在2 kHz與20 kHz操作下的正確輸出結果。此外，研究使用不同的光偵測器，對光電邏輯閘輸出特性之影響，發現以光電晶體作為光接受器較為節能，¬以光二極體作為光接受器則有較快的傳輸速度。
最後，將基於光電邏輯閘的成果，開發光電SR閂鎖器，在展示光電NOR閘的輸出特性後，將兩光電NOR閘的輸出與輸入相接，形成光電SR閂鎖器電路。透過邏輯功能驗證量測，發現提升Set/Reset光輸入脈衝強度，可有效提升光電SR閂鎖器的操作速度，本研究成功展示光電SR閂鎖器於5 mW光脈衝強度下，操作在0.2 MHz的正確輸出結果，為學界首次以發光電晶體整合電路製作出光電SR閂鎖器之研究。

關鍵字

發光電晶體 ； 光電晶體 ； 光二極體 ； 光電積體整合電路 ； 小訊號模型 ； 光電邏輯閘 ； 光電SR閂鎖器

並列摘要

Owing to the pico-second level of recombination life time of light emitting transistor (LET), it has high optical modulation bandwidth and dual-outputs (electrical and optical) characteristic. Besides, the structure of LET can function as light transmitter, modulator, and light receiver at the same time. With all advantages above, it makes LET as a perfect building block for next generation Opto-Electronic Integrated Circuits (OEICs).
The first part of this thesis introduces and compares the characteristics of LET serving as different light receivers. Compared with photodiode (PD), heterojunction phototransistor (HPT) has internal gain mechanism, and thus it has larger responsivity, while the more complex structure and operation mechanism slow down the optical modulation speed. We have proposed a brand new equivalent small-signal model of two-terminal phototransistor to examine the crucial parameters affecting the optical modulation frequency. We have obtained that reducing size and applying larger light power promote HPT with higher operating speed. As for PD, its optical modulation speed also benefits from size scaling.
In the second part, we have demonstrated the optical logic composed of a light receiver and a LET, and it can simultaneously output the electrical NAND gate and optical AND gate. The optical logic operating at 2 kHz and 20 kHz have been presented. Moreover, we are committed to studying the signal transmission parameters using different light detector. It is obtained that the optical logic using HPT has lower power consumption while that using PD has faster transmission ability.
The last part of thesis shows the development of optical SR Latch based on the results of optical logic gates. After presenting the correct function of optical logic gate providing electrical NOR gate, the output terminals and input terminals of two logic gates are connected to each other to integrate as an optical SR Latch. Through the function test to the SR Latch, enhancing the applied Set/Reset optical pulse power can improve its operating speed, and we have successfully demonstrated the latch ability at 0.2 MHz under 5 mW applied power. This study is the very first case realizing optical SR Latch in the field of LET integrated circuits in academia.

並列關鍵字

light emitting transistor ； heterojunction phototransistor ； photodiode ； Opto-Electronic Integrated Circuits ； equivalent small-signal model ； optical logic gate ； optical SR Latch

參考文獻

1. Cisco Visual Networking Index: Forecast and Trends, 2017–2022 White Paper. Available from: https://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/white-paper-c11-741490.html.

2. Gartner Says the Internet of Things Installed Base Will Grow to 26 Billion Units By 2020. Available from: https://attivonetworks.com/gartner-says-the-internet-of-things-installed-base-will-grow-to-26-billion-units-by-2020/.

3. Challenges and Solutions for EDA of 3D Chip Stacks. Available from: https://www.3dincites.com/2016/05/challenges-and-solutions-for-eda-of-3d-chip-stacks/.

4. Augustin, L.M., et al., InP-based generic foundry platform for photonic integrated circuits. IEEE journal of selected topics in quantum electronics, 2017. 24(1): p. 1-10.

5. Van Campenhout, J., et al., Electrically pumped InP-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit. Optics express, 2007. 15(11): p. 6744-6749.