可調式影像編碼器與解碼器之分析與積體電路架構設計

Analysis and VLSI Architecture Design of Scalable Video Coding Encoder and Decoder

莊子德(Tzu-Der Chuang)

指導教授 ： 陳良基

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2010年)

https://doi.org/10.6342/NTU.2010.01365

摘要

隨著影像編碼技術的進步，人們對於高品質、高清晰度影像以及影像可調式功能的需求，推動了可調式視訊編碼標準(Scalable Video Coding, SVC)的制定。在本論文中，我們主要的目標是實現出一個能支援Full HD高清晰度的SVC以及H.264/AVD High Profile的影像編碼器，以及一個最高能支援Quad Full HD的SVC/MVC(多視角影像編碼)/H.264 High Profile影像解碼器。本論文分為三部分，分別是SVC編解碼工具設計、影像編碼器晶片實現、以及影像解碼器晶片實現。在每一個部分我們會討論其硬體演算法以及架構設計，以及其對於記憶體頻寬、計算複雜度、硬體面積、以及耗電等影響。

在第一部份，我們分析了可調式影像編解碼工具並提出各個編解碼工具的硬體架構設計。對於時間可調性，我們分析了雙向式畫面預測架構對於視訊編碼器的影響，並針對其運算特性提出了畫面層級的資料重複利用，降低記憶體頻寬需求。對於空間可調性，我們首先分析SVC層間預測的特性以及硬體需求。對於層間畫面重新取樣，我們將畫面層級運算降到區塊層級運算，減低34%解碼記憶體頻寬以及36%的整體解碼運算時間。而因層間預測所需要的大量運算量，我們分析其運算特性，提出低複雜度的移動估計演算法及硬體架構，有效率的提供所需運算量。結合時間及空間可調性，我們也設計出一個可調變的階級式移動估計演算法及硬體架構，結合可重整硬體架構，我們能支援SVC所需的各種編碼設定。而對於畫質可調性，我們支援了CGS, MGS, FGS三種編碼工具。對於CGS, MGS解碼，我們改變解碼的流程，提出層交錯解碼流程，減少41~51%的解碼頻寬。對於FGS編碼，我們分析了編碼流程，並提出三種資料先處理流程及架構，減少92% FGS所需的頻寬。

在第二部分，我們把重點放在實現一個Full HD H.264 High Profile與 SVC影像編碼器。在空間性預測上，我們也分析了運算的資料依賴性並對此提出適合硬體運算的演算法，硬體設計上也配合可重組化的硬體架構來實現。然後，我們整合所有提出的硬體架構和SVC編碼工具，實現一個單晶片影像編碼器。在系統設計層級，我們所提出的畫面平行編碼架構以及畫面層級資料重複利用減少了25~50％的記憶體頻寬。此外，為支持FGS，我們也提出綜合區塊層級以及畫面層級的管線架構。在模組設計層級，我們整合了論文第一部分所提出的編碼工具。這些架構可減少70％移動估計所需頻寬和90％的FGS所需的頻寬。而在非整數點移動估計，我們的架構提供了比傳統架構高7.2倍的處理能力。此晶片使用了UMC 90奈米製程，能在120/166MHz的運作頻率支援H.264與SVC的影像編碼。
在論文的最後一部分，因為支援Quad Full HD所會產生的高運算量跟高頻寬需求，我們也提出相對的硬體架構。在熵解碼器當中的CABAD解碼器，我們分析其運算瓶頸，並且利用平行運算與分支選取等方法，提出了一個具有現行架構2.3 ~4.9倍的運算量的CABAD解碼器。為了減少頻寬，我們提出了一個雙關聯快取移動補償架構與低DRAM存取延遲的資料擺放及資料存取方法。此架構能減少73％的移動補償所需頻寬。最後，我們提出全球第一個59.5毫瓦單晶片高性能、低頻寬、低耗電，能支援SVC/MVC/H.264的多標準視頻解碼器。我們採用了多項低耗電技巧，減少47％的功率消耗。因為支援SVC的解碼能力，它能解碼各種不同畫面大小的影像，並提供不同的畫面頻率以及畫面品質。此晶片也支援MVC，能提供各種三維影像相關應用。此晶片使用了UMC 90奈米製程，能支援從低功耗攜帶式設備到高階Quad Full HD和3DTV的應用。

關鍵字

可調式影像 ； 編碼器 ； 解碼器

並列摘要

With advances in video coding technology, the demand of high quality, high definition, and scalable functionality of video encourages the developments of newest video coding standards — H.264/AVC scalable extension, the scalable video coding (SVC). In this dissertation, we aim to build a Full HD SVC/H.264 High Profile video encoder and a SVC/MVC/H.264 Quad Full HD video decoder. We classify this dissertation into three part, SVC coding tools, high definition video encoder, and high definition video decoder. In each part, the discussion includes algorithm design, system-level architecture design, and module-level architecture design for memory bandwidth, computation complexity, hardware cost, and power consumption issues.

In the first part, the analysis and architecture design of the scalability coding tools are presented. For the temporal scalability, the data independency of the hierarchical B-frame is utilized to improve the level of data reuse from MB level to frame level. For the spatial scalability, the data flow and the impact of the inter-layer prediction are analyzed. In SVC encoder, low complexity and low cost FME algorithm and architecture with supporting SVC inter-layer prediction is described. In SVC decoder, we propose the MB-level on-the-fly padding and on-line upsampling which convert the frame-level resampling operation into MB-level processes. 34% of decoding bandwidth and 36% of extra processing cycles are reduced. Considering the characteristic of the temporal and spatial scalabilities, an adaptive spatial-temporal hierarchical ME with reconfigurable architecture is contributed to support the diverse coding configurations. For the quality scalability, the FGS, MGS and CGS are discussed. Three design techniques, the scan bucket preprocessing, early context modeling and first scan pre-encoding are proposed to eliminate the irregular frame-level access of FGS and reduce 92% of memory bandwidth. For CGS and MGS decoding, we propose the layer-interleaving decoding scheme which reduces 51% and 41% of total decoding bandwidth compared with the typical layer-by-layer decoding scheme.

In the second part, we focus on the implementation of a HD 1080p H.264 High Profile and SVC video encoder. A hardware oriented high throughput intra prediction algorithm and VLSI architecture are provided. Then, we integrate all the proposed hardware architectures of SVC and High Profile coding tools into a single chip video encoder. Two-level design techniques are provided. On the system level, the frame-parallel encoding structure and the frame-level data reuse scheme for B-frame coding are proposed to reduce 25%~50% of memory bandwidth of ME. In addition, to support SVC quality scalability, the two-frame pipeline architecture is also proposed for frame-level FGS coding. On the module level, the proposed algorithms and architectures of scalable coding tools in the first part are implemented. These architectures achieve 70% and 90% of bandwidth reduction in IME and FGS, and 7.2X processing throughput in FME. This chip is implemented on a 16.76mm2 die with UMC 90nm process and dissipates 306/411mW at 120/166MHz for high profile and SVC encoding.

In the last part of dissertation, the processing throughput limitation of CABAD entropy decoding and the bandwidth requirement of motion compensation for Quad Full HD and multi-view video decoding are discussed. For entropy decoding, we propose a branch selection multi-symbol CABAD architecture which has 2.3~4.9X greater throughput than previous works. To reduce the bandwidth, we propose a two-way associative cache-based motion compensation architecture with the DRAM-friendly access strategy and low precharge/active data mapping. A total of 73% of motion compensation bandwidth is saved. At the end, a 59.5mW worldwide first single-chip high-performance, low-bandwidth, low power consumption Multi-standard video decoder for H.264/AVC High Profile, SVC High Profile, and MVC High Profile is presented. Two-level power reduction strategies are applied to reduce 47% of power consumption. Only 59.5mW is required for QFHD single view video decoding. With the ability to decode SVC, it supports spatial scalability from QCIF to 1080p HD, and quality scalability to provide various bitrate-quality-power decoding trade-off points. View scalability for 3D and multi-view applications is also provided with MVC decoding. The chip is implemented on an 8.53mm2 die with UMC 90nm CMOS. The proposed decoder can support applications from low-power portable devices to high-end QFHD and 3DTV.

並列關鍵字

SVC ； encoder ； decoder

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